SN74AUC1G74_07 Datasheet, PDF (1/15 Pages) Texas Instruments – SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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SN74AUC1G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES537D – DECEMBER 2003 – REVISED JUNE 2007
FEATURES
• Available in the Texas Instruments
NanoFree™ Package
• Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
• I_off Supports Partial-Power-Down Mode
Operation
• Sub-1-V Operable
• Max t_pd of 1.5 ns at 1.8 V
DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
• Low Power Consumption, 10-μA Max I_CC
• ±8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
RSE PACKAGE
(TOP VIEW)
YZP OR YZT PACKAGE
(BOTTOM VIEW)
CLK
1
D
2
Q
3
GND
4
8
V_CC
CLK 1
D2
7
PRE
Q3
6
CLR
GND
4
5
Q
8
V_CC
7 PRE
6 CLR
5Q
V_CC 8
4 GND
GND 4 5 Q
Q ^{3 6} CLR
D ² 7 PRE
CLK
1 8 _VCC
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V V_CC, but is designed
specifically for 1.65-V to 1.95-V V_CC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for
higher frequencies, the CLR input overrides the PRE input when they are both low.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated