SN74AUC1G126 Datasheet, PDF (1/12 Pages) Texas Instruments – SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

D Available in the Texas Instruments
NanoStar and NanoFree Packages
D Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D I_off Supports Partial-Power-Down Mode
Operation
D Sub 1-V Operable
D Max t_pd of 2.5 ns at 1.8 V
D Low Power Consumption, 10-µA Max I_CC
D ±8-mA Output Drive at 1.8 V
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN74AUC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES383F – MARCH 2002 – REVISED AUGUST 2003
DBV OR DCK PACKAGE
(TOP VIEW)
OE 1
A2
GND 3
5 V_CC
4Y
YEP OR YZP PACKAGE
(BOTTOM VIEW)
GND 3 4 Y
A2
OE 1 5 V_CC
description/ordering information
This bus buffer gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC
operation.
The SN74AUC1G126 is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING‡
–40°C to 85°C
NanoStar
WCSP (DSBGA) – YEP
NanoFree
WCSP (DSBGA) – YZP (Pb-free)
Tape and reel SN74AUC1G126YEPR
Tape and reel SN74AUC1G126YZPR
_ _ _UN_
SOT (SOT-23) – DBV
Tape and reel SN74AUC1G126DBVR U26_
SOT (SC-70) – DCK
Tape and reel SN74AUC1G126DCKR UN_
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at}
www.ti.com/sc/package.
‡ _{DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.}
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2003, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1