SN74AUC1G04 Datasheet, PDF (1/12 Pages) Texas Instruments – SINGLE INVERTER GATE

SN74AUC1G04
SINGLE INVERTER GATE
D Available in the Texas Instruments
NanoStar and NanoFree Packages
D Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D I_off Supports Partial-Power-Down Mode
Operation
D Sub 1-V Operable
D Max t_pd of 2.2 ns at 1.8 V
D Low Power Consumption, 10-µA Max I_CC
D ±8-mA Output Drive at 1.8 V
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SCES370L − SEPTEMBER 2001 − REVISED NOVEMBER 2003
DBV OR DCK PACKAGE
(TOP VIEW)
NC 1
A2
GND 3
5 V_CC
4Y
NC − No internal connection
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
GND 3 4 Y
A2
DNU 1 5 V_CC
DNU − Do not use
description/ordering information
This single inverter gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V
V_CC operation.
The SN74AUC1G04 performs the Boolean function Y = A.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING‡
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA
SN74AUC1G04YEAR
−40°C to 85°C
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Tape and reel
SN74AUC1G04YZAR
SN74AUC1G04YEPR
_ _ _UC_
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
SN74AUC1G04YZPR
SOT (SOT-23) − DBV
Tape and reel SN74AUC1G04DBVR U04_
SOT (SC-70) − DCK
Tape and reel SN74AUC1G04DCKR UC_
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at}
www.ti.com/sc/package.
‡ _{DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.}
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2003, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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