SN74AS195 Datasheet, PDF (1/8 Pages) Texas Instruments – 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

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SDAS138B – DECEMBER 1983 – REVISED JANUARY 1995
C• Parallel-to-Serial, Serial-to-Parallel
Conversions
D OR N PACKAGE
(TOP VIEW)
D^{• Parallel Synchronous Loading}
• J and K Inputs to First Stage
• ERight Shift Only With Complementary
Outputs on Last Stage
• Direct Overriding Clear
• FPackage Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
CLR 1
J2
K3
A4
B5
C6
T ^D7
GND 8
16 V_CC
15 Q_A
14 Q_B
13 Q_C
12 Q_D
11 Q_D
10 CLK
9 SH/LD
G
description
H ^I _{This 4-bit bidirectional universal shift register features parallel (A, B, C, D) inputs, parallel (QA, QB, QC, QD, QD)}
P ^{I I I} _{outputs, J-K serial (J, K) inputs, shift/load control (SH/LD) input, and a direct overriding clear (CLR). The}
registers have two modes of operation:
•
•
Q^{Parallel (broadside) load}
I
Shift (in the direction Q_A toward Q_D)
R^{Parallel loading is accomplished by applying the four bits of data and taking SH/LD low. The data is loaded into}
the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During
Q^{loading, serial data flow is inhibited.}
Shifting is accomplished synchronously when SH/LD is high. Serial data for this mode is entered at the J-K
R^{inputs. These inputs permit the first stage to perform as a J-K, D-, or T-type flip-flop as shown in the function}
table.
SS
The SN74AS195 is characterized for operation from 0°C to 70°C.
CLR SH/LD CLK
L
X
X
H
L
↑
H
H
L
H
H
↑
H
H
↑
H
H
↑
H
H
↑
INPUTS
SERIAL
J
K
X
X
X
X
X
X
L
H
L
L
H
H
H
L
FUNCTION TABLE
PARALLEL
A
B
C
D
X
X
X
X
a
b
c
d
X
XX
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OUTPUTS
QA
L
a
QA0
QA0
L
H
QAN
QB
L
bc
QB0
QA0
QAn
QAn
QAn
QC
L
QC0
QBn
QBn
QBn
QBn
QD
L
d
QD0
QCn
QCn
QCn
QCn
QD
H
d
QD0
QCn
QCn
QCn
QCn
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