SN74ALVTH16827_07 Datasheet, PDF (1/16 Pages) Texas Instruments – 2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

D State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus ™ Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V_CC )
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D High Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V V_CC)
D Power Off Disables Outputs, Permitting
Live Insertion
D High-Impedance State During Power Up
and Power Down Prevents Driver Conflict
D Uses Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
D Auto3-State Eliminates Bus Current
Loading When Output Exceeds V_CC + 0.5 V
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model; and Exceeds 1000 V
Using Charged-Device Model, Robotic
Method
D Flow-Through Architecture Facilitates
Printed Circuit Board Layout
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
SN54ALVTH16827, SN74ALVTH16827
2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES076E – JULY 1996 – REVISED DECEMBER 1998
SN54ALVTH16827 . . . WD PACKAGE
SN74ALVTH16827 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE1 1
1Y1 2
1Y2 3
GND 4
1Y3 5
1Y4 6
V_CC 7
1Y5 8
1Y6 9
1Y7 10
GND 11
1Y8 12
1Y9 13
1Y10 14
2Y1 15
2Y2 16
2Y3 17
GND 18
2Y4 19
2Y5 20
2Y6 21
V_CC 22
2Y7 23
2Y8 24
GND 25
2Y9 26
2Y10 27
2OE1 28
56 1OE2
55 1A1
54 1A2
53 GND
52 1A3
51 1A4
50 V_CC
49 1A5
48 1A6
47 1A7
46 GND
45 1A8
44 1A9
43 1A10
42 2A1
41 2A2
40 2A3
39 GND
38 2A4
37 2A5
36 2A6
35 V_CC
34 2A7
33 2A8
32 GND
31 2A9
30 2A10
29 2OE2
description
The ’ALVTH16827 devices are 20-bit buffers/line drivers designed for 2.5-V or 3.3-V V_CC operation, but with
the capability to provide a TTL interface to a 5-V system environment.
The devices are composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer
section, the two output-enable (1OE1 and 1OE2, or 2OE1 and 2OE2) inputs must be low for the corresponding
Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the
high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright © 1998, Texas Instruments Incorporated
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