SN74ALVCHR16601 Datasheet, PDF (1/9 Pages) Texas Instruments – 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SN74ALVCHR16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES123G – SEPTEMBER 1997 – REVISED JUNE 1999
D Member of the Texas Instruments
Widebus ™ Family
D EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D UBT ™ (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
D Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and 300-mil Shrink
Small-Outline (DL) Packages
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR,
the DGVR package is abbreviated to VR, and
the DLR package is abbreviated to LR.
description
This 18-bit universal bus transceiver is designed
for 1.65-V to 3.6-V V_CC operation.
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
OEAB 1
LEAB 2
A1 3
GND 4
A2 5
A3 6
V_CC 7
A4 8
A5 9
A6 10
GND 11
A7 12
A8 ¹³
A9 ¹⁴
A10 ¹⁵
A11 ¹⁶
A12 ¹⁷
GND ¹⁸
A13 ¹⁹
A14 ²⁰
A15 ²¹
V_CC ²²
A16 ²³
A17 ²⁴
GND ²⁵
A18 ²⁶
OEBA ²⁷
LEBA ²⁸
56 CLKENAB
55 CLKAB
54 B1
53 GND
52 B2
51 B3
50 V_CC
49 B4
48 B5
47 B6
46 GND
45 B7
44 _B8
43 _B9
42 _B10
41 _B11
40 _B12
39 _GND
38 _B13
37 _B14
36 _B15
35 _VCC
34 _B16
33 _B17
32 _GND
31 _B18
30 _CLKBA
29 _CLKENBA
The SN74ALVCHR16601 combines D-type latches and D-type flip-flops to allow data flow in transparent,
latched, clocked, and clock-enabled modes.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and
CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is low, the outputs are active. When
OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.
The outputs include equivalent 26-Ω series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC, and UBT are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
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