SN74ALVCH373 Datasheet, PDF (1/12 Pages) Texas Instruments – OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

D Operates From 1.65 V to 3.6 V
D Max t_pd of 3.3 ns at 3.3 V
D ±24-mA Output Drive at 3.3 V
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN74ALVCH373
OCTAL TRANSPARENT DĆTYPE LATCH
WITH 3ĆSTATE OUTPUTS
SCES116G − JULY 1997 − REVISED AUGUST 2003
DGV, DW, OR PW PACKAGE
(TOP VIEW)
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 V_CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
description/ordering information
This octal transparent D-type latch is designed for 1.65-V to 3.6-V V_CC operation.
The SN74ALVCH373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − DW
Tube
Tape and reel
SN74ALVCH373DW
SN74ALVCH373DWR
ALVCH373
−40°C to 85°C
TSSOP − PW
TVSOP − DGV
Tape and reel
Tape and reel
SN74ALVCH373PWR VB373
SN74ALVCH373DGVR VB373
VFBGA − GQN
Tape and reel
VFBGA − ZQN (Pb-free)
SN74ALVCH373GQNR
VB373
SN74ALVCH373ZQNR
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2003, Texas Instruments Incorporated
1