SN74ALVCH16973 Datasheet, PDF (1/13 Pages) Texas Instruments – 8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH FOUR INDEPENDENT BUFFERS

www.ti.com
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
FEATURES
• Member of the Texas Instruments Widebus™
Family
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This device contains four independent noninverting
buffers and an 8-bit noninverting bus transceiver and
D-type latch, designed for 1.65-V to 3.6-V V_CC
operation.
The SN74ALVCH16973 is particularly suitable for
demultiplexing an address/data bus into a dedicated
address bus and dedicated data bus. The device is
used where there is asynchronous bidirectional
communication between the A and B data bus, and
the address signals are latched and buffered on the
Q bus. The control-function implementation minimizes
external timing requirements.
This device can be used as one 4-bit buffer, one 8-bit
transceiver, or one 8-bit latch. It allows data
transmission from the A bus to the B bus or from the
B bus to the A bus, depending on the logic level at
the direction-control (DIR) input. The transceiver
output-enable (TOE) input can be used to disable the
transceivers so that the A and B buses effectively are
isolated.
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
TOE 1
D1 2
A1 3
GND 4
Y1 5
A2 6
V_CC 7
D2 8
A3 9
GND 10
Y2 11
A4 12
D3 13
A5 14
GND 15
Y3 16
A6 17
V_CC 18
D4 19
A7 20
GND 21
A8 22
Y4 23
LE 24
48 DIR
47 B1
46 Q1
45 GND
44 B2
43 Q2
42 V_CC
41 B3
40 Q3
39 GND
38 B4
37 Q4
36 B5
35 Q5
34 GND
33 B6
32 Q6
31 V_CC
30 B7
29 Q7
28 GND
27 Q8
26 B8
25 LOE
T_A
-40°C to 85°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
SSOP - DL
Tube
Tape and reel
SN74ALVCH16973DL
SN74ALVCH16973DLR
TSSOP - DGG
Tape and reel
SN74ALVCH16973DGGR
TVSOP - DGV
Tape and reel
SN74ALVCH16973DGVR
TOP-SIDE MARKING
ALVCH16973
ALVCH16973
VH973
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2004, Texas Instruments Incorporated