SN74ALVCH16903 Datasheet, PDF (1/12 Pages) Texas Instruments – 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS

SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
SCES095C – MARCH 1997 – REVISED MAY 1998
D Member of the Texas Instruments
Widebus™ Family
D EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D Checks Parity
D Able to Cascade With a Second
SN74ALVCH16903
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
description
This 12-bit universal bus driver is designed for
2.3-V to 3.6-V V_CC operation.
The SN74ALVCH16903 has dual outputs and can
operate as a buffer or an edge-triggered register.
In both modes, parity is checked on APAR, which
arrives one cycle after the data to which it applies.
The YERR output, which is produced one cycle
after APAR, is open drain.
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
OE 1
1Y1 2
1Y2 3
GND 4
2Y1 5
2Y2 6
V_CC 7
3Y1 8
3Y2 9
4Y1 10
GND 11
4Y2 12
5Y1 13
5Y2 14
6Y1 15
6Y2 16
7Y1 17
GND 18
7Y2 19
8Y1 20
8Y2 21
V_CC 22
9Y1 23
9Y2 24
GND 25
10Y1 26
10Y2 27
PAROE 28
56 CLK
55 1A
54 11A/YERREN
53 GND
52 11Y1
51 11Y2
50 V_CC
49 2A
48 3A
47 4A
46 GND
45 12A
44 12Y1
43 12Y2
42 5A
41 6A
40 7A
39 GND
38 APAR
37 8A
36 YERR
35 V_CC
34 9A
33 MODE
32 GND
31 10A
30 PARI/O
29 CLKEN
MODE selects one of the two data paths. When MODE is low, the device operates as an edge-triggered register.
On the positive transition of the clock (CLK) input and when the clock-enable (CLKEN) input is low, data set up
at the A inputs is stored in the internal registers. On the positive transition of CLK and when CLKEN is high, only
data set up at the 9A–12A inputs is stored in their internal registers. When MODE is high, the device operates
as a buffer and data at the A inputs passes directly to the outputs. 11A/YERREN serves a dual purpose; it acts
as a normal data bit and also enables YERR data to be clocked into the YERR output register.
When used as a single device, parity output enable (PAROE) must be tied high; when parity input/output
(PARI/O) is low, even parity is selected and when PARI/O is high, odd parity is selected. When used in pairs
and PAROE is low, the parity sum is output on PARI/O for cascading to the second SN74ALVCH16903. When
used in pairs and PAROE is high, PARI/O accepts a partial parity sum from the first SN74ALVCH16903.
A buffered output-enable (OE) input can be used to place the 24 outputs and YERR in either a normal logic state
(high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive
bus lines without need for interface or pullup components.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
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