SN74ALVCH16901DGGR Datasheet, PDF (1/14 Pages) Texas Instruments – 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS

SN74ALVCH16901
18ĆBIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010F − JULY 1995 − REVISED SEPTEMBER 2004
D Member of the Texas Instruments
Widebus Family
D UBT  Transceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched, or
Clocked Mode
D Operates From 1.65 V to 3.6 V
D Max t_pd of 4.4 ns at 3.3 V
D ±24-mA Output Drive at 3.3 V
D Simultaneously Generates and Checks
Parity
D Option to Select Generate Parity and Check
or Feed-Through Data/Parity in A-to-B or
B-to-A Directions
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
description/ordering information
This 18-bit (dual-octal) noninverting registered
transceiver is designed for 1.65-V to 3.6-V V_CC
operation.
The SN74ALVCH16901 is a dual 9-bit to dual 9-bit
parity transceiver with registers. The device can
operate as a feed-through transceiver or it can
generate/check parity from the two 8-bit data
buses in either direction.
DGG PACKAGE
(TOP VIEW)
1CLKENAB 1
LEAB 2
CLKAB 3
1ERRA 4
1APAR 5
GND 6
1A1 7
1A2 8
1A3 9
V_CC 10
1A4 11
1A5 12
1A6 13
GND 14
1A7 15
1A8 16
2A1 17
2A2 18
GND 19
2A3 20
2A4 21
2A5 22
V_CC 23
2A6 24
2A7 25
2A8 26
GND 27
2APAR 28
2ERRA 29
OEAB 30
SEL 31
2CLKENAB 32
64 1CLKENBA
63 LEBA
62 CLKBA
61 1ERRB
60 1BPAR
59 GND
58 1B1
57 1B2
56 1B3
55 V_CC
54 1B4
53 1B5
52 1B6
51 GND
50 1B7
49 1B8
48 2B1
47 2B2
46 GND
45 2B3
44 2B4
43 2B5
42 V_CC
41 2B6
40 2B7
39 2B8
38 GND
37 2BPAR
36 2ERRB
35 OEBA
34 ODD/EVEN
33 2CLKENBA
The SN74ALVCH16901 features independent
clock (CLKAB or CLKBA), latch-enable (LEAB or
LEBA), and dual 9-bit clock-enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and
parity-select (ODD/EVEN) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The
direction of data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled. When
SEL is high, the parity functions are disabled, and the device acts as an 18-bit registered transceiver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C TSSOP − DGG
Tape and reel SN74ALVCH16901DGGR ALVCH16901
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and UBT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2004, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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