SN74ALVCH16832 Datasheet, PDF (1/9 Pages) Texas Instruments – 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS

SN74ALVCH16832
1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES098D – MAY 1997 – REVISED FEBRUARY 1999
D Member of the Texas Instruments
Widebus ™ Family
D EPIC ™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Packaged in Thin Shrink Small-Outline
Package
description
This 1-bit to 4-bit address register/driver is
designed for 1.65-V to 3.6-V V_CC operation. This
device is ideal for use in applications in which a
single address bus is driving four separate
memory locations. The SN74ALVCH16832 can
be used as a buffer or a register, depending on the
logic level of the select (SEL) input.
When SEL is a logic high, the device is in the buffer
mode. The outputs follow the inputs and are
controlled by the two output-enable (OE) inputs.
Each OE controls two groups of seven outputs.
When SEL is a logic low, the device is in the
register mode. The register is an edge-triggered
D-type flip-flop. On the positive transition of the
clock (CLK) input, data at the A inputs is stored in
the internal registers. OE operates the same as in
the buffer mode.
DGG PACKAGE
(TOP VIEW)
4Y1 1
3Y1 2
GND 3
2Y1 4
1Y1 5
V_CC 6
A1 7
GND 8
A2 9
GND 10
A3 11
V_CC 12
NC 13
GND 14
CLK 15
OE1 16
OE2 17
SEL 18
GND 19
A4 20
A5 21
V_CC 22
GND 23
A6 24
GND 25
A7 26
V_CC 27
4Y7 28
3Y7 29
GND 30
2Y7 31
1Y7 32
64 1Y2
63 2Y2
62 GND
61 3Y2
60 4Y2
59 V_CC
58 1Y3
57 2Y3
56 GND
55 3Y3
54 4Y3
53 GND
52 V_CC
51 GND
50 1Y4
49 2Y4
48 3Y4
47 4Y4
46 GND
45 1Y5
44 2Y5
43 V_CC
42 3Y5
41 4Y5
40 GND
39 GND
38 V_CC
37 1Y6
36 2Y6
35 GND
34 3Y6
33 4Y6
When OE is a logic low, the outputs are in a normal
logic state (high or low logic level). When OE is a
logic high, the outputs are in the high-impedance
state.
NC – No internal connection
Neither SEL nor OE affect the internal operation of the flip-flops. Old data can be retained or new data can be
entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16832 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
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