SN74ALVCH16373_02 Datasheet, PDF (1/7 Pages) Texas Instruments – 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES020F – JULY 1995 – REVISED MAY 2002
D Member of the Texas Instruments
Widebus  Family
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DGG OR DL PACKAGE
(TOP VIEW)
1OE 1
1Q1 2
1Q2 3
GND 4
1Q3 5
1Q4 6
V_CC 7
1Q5 8
48 1LE
47 1D1
46 1D2
45 GND
44 1D3
43 1D4
42 V_CC
41 1D5
description
1Q6 9
GND 10
40 1D6
39 GND
This 16-bit transparent D-type latch is designed
for 1.65-V to 3.6-V V_CC operation.
The SN74ALVCH16373 is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
This device can be used as two 8-bit latches or
one 16-bit latch. When the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the levels set up at the D inputs.
1Q7 11
1Q8 12
2Q1 13
2Q2 14
GND 15
2Q3 16
2Q4 17
V_CC 18
2Q5 19
2Q6 20
GND 21
38 1D7
37 1D8
36 2D1
35 2D2
34 GND
33 2D3
32 2D4
31 V_CC
30 2D5
29 2D6
28 GND
A buffered output-enable (OE) input can be used
2Q7 22 27 2D7
to place the eight outputs in either a normal logic
2Q8 23 26 2D8
state (high or low logic levels) or the
2OE 24 25 2LE
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not affect internal operations of the latch. Old data
can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40°C to 85°C
SSOP – DL
TSSOP – DGG
Tube
Tape and reel
Tape and reel
SN74ALVCH16373DL
SN74ALVCH16373DLR
SN74ALVCH16373DGGR
ALVCH16373
ALVCH16373
VFBGA – GQL Tape and reel SN74ALVCH16373KR
VH373
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design}
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2002, Texas Instruments Incorporated
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