SN74ALVCH16271_04 Datasheet, PDF (1/15 Pages) Texas Instruments – 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS

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SN74ALVCH16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017G – JULY 1995 – REVISED SEPTEMBER 2004
FEATURES
• Member of the Texas Instruments Widebus™
Family
DGG OR DL PACKAGE
(TOP VIEW)
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
This 12-bit to 24-bit bus exchanger is designed for
1.65-V to 3.6-V V_CC operation.
The SN74ALVCH16271 is intended for applications in
which two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path. This
device is particularly suitable as an interface
between conventional DRAMs and high-speed
microprocessors.
A data is stored in the internal A-to-B registers on the
low-to-high transition of the clock (CLK) input,
provided that the clock-enable (CLKENA) inputs are
low. Proper control of these inputs allows two
sequential 12-bit words to be presented as a 24-bit
word on the B port.
Transparent latches in the B-to-A path allow
asynchronous operation to maximize memory access
throughput. These latches transfer data when the
latch-enable (LE) inputs are low. The select (SEL)
line selects 1B or 2B data for the A outputs. Data flow
is controlled by the active-low output enables (OEA,
OEB).
OEA 1
LE1B 2
2B3 3
GND 4
2B2 5
2B1 6
V_CC 7
A1 8
A2 9
A3 10
GND 11
A4 12
A5 13
A6 14
A7 15
A8 16
A9 17
GND 18
A10 19
A11 20
A12 21
V_CC 22
1B1 23
1B2 24
GND 25
1B3 26
LE2B 27
SEL 28
56 OEB
55 CLKENA2
54 2B4
53 GND
52 2B5
51 2B6
50 V_CC
49 2B7
48 2B8
47 2B9
46 GND
45 2B10
44 2B11
43 2B12
42 1B12
41 1B11
40 1B10
39 GND
38 1B9
37 1B8
36 1B7
35 V_CC
34 1B6
33 1B5
32 GND
31 1B4
30 CLKENA1
29 CLK
line
space
To ensure the high-impedance state during power up or power down, the output enables should be tied to V_CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
T_A
PACKAGE ⁽¹⁾
-40°C to 85°C
SSOP - DL
TSSOP - DGG
Tube
Tape and reel
Tape and reel
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SN74ALVCH16271DL
SN74ALVCH16271DLR
ALVCH16271
SN74ALVCH16271DGGR ALVCH16271
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2004, Texas Instruments Incorporated