SN74ALVCH16270 Datasheet, PDF (1/10 Pages) Texas Instruments – 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

SN74ALVCH16270
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES028F – JULY 1995 – REVISED FEBRUARY 1999
D Member of the Texas Instruments
Widebus ™ Family
DGG OR DL PACKAGE
(TOP VIEW)
D EPIC ™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
OEA 1
CLKEN1B 2
2B3 3
GND 4
2B2 5
2B1 6
V_CC 7
A1 8
A2 9
56 OEB
55 CLKENA2
54 2B4
53 GND
52 2B5
51 2B6
50 V_CC
49 2B7
48 2B8
JESD 17
D Package Options Include Plastic Shrink
A3 10
GND 11
47 2B9
46 GND
Small-Outline (DL) and Thin Shrink
A4 12 45 2B10
Small-Outline (DGG) Packages
A5 13 44 2B11
A6 14 43 2B12
description
A7 15 42 1B12
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V V_CC operation.
A8 16
A9 17
GND 18
41 1B11
40 1B10
39 GND
The SN74ALVCH16270 is used in applications in
A10 19 38 1B9
which data must be transferred from a narrow
A11 20 37 1B8
high-speed bus to a wide lower-frequency bus.
A12 21 36 1B7
The device provides synchronous data exchange
between the two ports. Data is stored in the
internal registers on the low-to-high transition of
the clock (CLK) input when the appropriate
CLKEN inputs are low. The select (SEL) line
selects 1B or 2B data for the A outputs. For data
transfer in the A-to-B direction, a two-stage
V_CC 22
1B1 23
1B2 24
GND 25
1B3 26
CLKEN2B 27
SEL 28
35 V_CC
34 1B6
33 1B5
32 GND
31 1B4
30 CLKENA1
29 CLK
pipeline is provided in the A-to-1B path, with a
single storage register in the A-to-2B path.
Proper control of the CLKENA inputs allows two sequential 12-bit words to be presented synchronously as a
24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). The control
terminals are registered to synchronize the bus-direction changes with CLK.
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon
as possible and OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active
state of the outputs cannot be determined prior to the arrival of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16270 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
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