SN74ALVCH162373 Datasheet, PDF (1/10 Pages) Texas Instruments – 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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FEATURES
• Member of the Texas Instruments Widebus™
Family
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
This 16-bit transparent D-type latch is designed for
1.65-V to 3.6-V V_CC operation.
The SN74ALVCH162373 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. This device can
be used as two 8-bit latches or one 16-bit latch.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is taken
low, the Q outputs are latched at the levels set up at
the D inputs.
A buffered output-enable (OE) input can be used to
place the eight outputs in either a normal logic state
(high or low logic levels) or the high-impedance state.
In the high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and the increased drive provide
the capability to drive bus lines without need for
interface or pullup components. OE does not affect
internal operations of the latch. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance state.
SN74ALVCH162373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES583A – JULY 2004 – REVISED OCTOBER 2004
DGG OR DL PACKAGE
(TOP VIEW)
1OE 1
1Q1 2
1Q2 3
GND 4
1Q3 5
1Q4 6
V_CC 7
1Q5 8
1Q6 9
GND 10
1Q7 11
1Q8 12
2Q1 13
2Q2 14
GND 15
2Q3 16
2Q4 17
V_CC 18
2Q5 19
2Q6 20
GND 21
2Q7 22
2Q8 23
2OE 24
48 _1LE
47 _1D1
46 _1D2
45 _GND
44 _1D3
43 _1D4
42 _VCC
41 _1D5
40 _1D6
39 _GND
38 _1D7
37 _1D8
36 2D1
35 _2D2
34 _GND
33 _2D3
32 _2D4
31 V_CC
30 _2D5
29 _2D6
28 _GND
27 2D7
26 2D8
25 2LE
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and
undershoot.
T_A
-40°C to 85°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
SSOP - DL
Tube
Tape and reel
SN74ALVCH162373DL
SN74ALVCH162373LR
TSSOP - DGG
Tape and reel
SN74ALVCH162373GR
VFBGA - GQL
Tape and reel
SN74ALVCH162373KR
TOP-SIDE MARKING
ALVCH162373
ALVCH162373
VH2373
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated