SN74ALVC74 Datasheet, PDF (1/8 Pages) Texas Instruments – DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

SN74ALVC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES109E – JULY 1997 – REVISED JANUARY 1999
D EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages
description
This dual positive-edge-triggered D-type flip-flop
is designed for 1.65-V to 3.6-V V_CC operation.
D, DGV, OR PW PACKAGE
(TOP VIEW)
1CLR ₁
1D 2
1CLK 3
1PRE 4
1Q 5
1Q 6
GND 7
14 ^V_CC
13 2CLR
12 2D
11 2CLK
10 2PRE
9 2Q
8 2Q
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input may be changed without affecting the levels at the outputs.
The SN74ALVC74 is characterized for operation from –40°C to 85°C.
logic symbol^†
FUNCTION TABLE
INPUTS
OUTPUTS
PRE CLR CLK D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H† H†
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0 Q0
† _{This configuration is unstable; that is, it does not}
persist when PRE or CLR returns to its inactive
(high) level.
4
1PRE
3
1CLK
2
1D
1
1CLR
10
2PRE
11
2CLK
12
2D
13
2CLR
S
C1
1D
R
5
1Q
6
1Q
9
2Q
8
2Q
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.}
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Copyright © 1999, Texas Instruments Incorporated
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