SN74ALVC164245DGGT Datasheet, PDF (1/15 Pages) Texas Instruments – 16-BIT 2.5-V 3.3-V 3.3V TO 5-V LEVEL-SHIFTING TRANSCEIVER

SN74ALVC164245
16ĆBIT 2.5ĆV TO 3.3ĆV/3.3ĆV TO 5ĆV LEVELĆSHIFTING TRANSCEIVER
WITH 3ĆSTATE OUTPUTS
SCAS416L − MARCH 1994 − REVISED FEBRUARY 2004
D Member of the Texas Instruments
Widebus Family
D Max t_pd of 5.8 ns at 3.3 V
D ±24-mA Output Drive at 3.3 V
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
description/ordering information
This 16-bit (dual-octal) noninverting bus
transceiver contains two separate supply rails.
B port has V_CCB, which is set to operate at 3.3 V
and 5 V. A port has V_CCA, which is set to operate
at 2.5 V and 3.3 V. This allows for translation from
a 2.5-V to a 3.3-V environment, and vice versa, or
from a 3.3-V to a 5-V environment, and vice versa.
The SN74ALVC164245 is designed for
asynchronous communication between data
buses.
To ensure the high-impedance state during power
up or power down, the output-enable (OE) input
should be tied to V_CC through a pullup resistor; the
minimum value of the resistor is determined by the
current-sinking capability of the driver.
DGG OR DL PACKAGE
(TOP VIEW)
1DIR 1
1B1 2
1B2 3
GND 4
1B3 5
1B4 6
(3.3 V, 5 V) V_CCB 7
1B5 8
1B6 9
GND 10
1B7 11
1B8 12
2B1 13
2B2 14
GND 15
2B3 16
2B4 17
(3.3 V, 5 V) V_CCB 18
2B5 19
2B6 20
GND 21
2B7 22
2B8 23
2DIR 24
48 1OE
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
42 V_CCA (2.5 V, 3.3 V)
41 1A5
40 1A6
39 GND
38 1A7
37 1A8
36 2A1
35 2A2
34 GND
33 2A3
32 2A4
31 V_CCA (2.5 V, 3.3 V)
30 2A5
29 2A6
28 GND
27 2A7
26 2A8
25 2OE
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SSOP − DL
Tube of 25
Reel of 1000
SN74ALVC164245DL
SN74ALVC164245DLR
ALVC164245
−40°C to 85°C TSSOP − DGG
Reel of 2000
Reel of 250
SN74ALVC164245DGGR
SN74ALVC164245DGGT
ALVC164245
VFBGA − GQL
Reel of 1000
VFBGA − ZQL (Pb-free)
SN74ALVC164245KR
74ALVC164245ZQLR
VC4245
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE DIR
OPERATION
L
L
B data to A bus
L
H A data to B bus
H
X
Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2004, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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