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SN74ALVC126 Datasheet, PDF (1/8 Pages) Texas Instruments – QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
D EPIC ™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
D, DGV, OR PW PACKAGE
(TOP VIEW)
1OE 1
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND 7
14 VCC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
description
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of
the driver.
The SN74ALVC126 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
logic symbol†
1
1OE
2
1A
4
2OE
5
2A
10
3OE
9
3A
13
4OE
12
4A
EN 1
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
1Y
6
2Y
8
3Y
11
4Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
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