SN74ALVC10 Datasheet, PDF (1/7 Pages) Texas Instruments – TRIPLE 3-INPUT POSITIVE-NAND GATE

SN74ALVC10
TRIPLE 3-INPUT POSITIVE-NAND GATE
D EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA
Per JESD 17
D Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages
SCES106D – JULY 1997 – REVISED OCTOBER 1998
D, DGV, OR PW PACKAGE
(TOP VIEW)
1A 1
1B 2
2A 3
2B 4
2C 5
2Y 6
GND 7
14 V_CC
13 1C
12 1Y
11 3C
10 3B
9 3A
8 3Y
description
This triple 3-input positive-NAND gate is designed for 1.65-V to 3.6-V V_CC operation.
The SN74ALVC10 performs the Boolean function Y = A • B • C or Y = A + B + C in positive logic.
The SN74ALVC10 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
A
B
C
OUTPUT
Y
H
H
H
L
L
X
X
H
X
L
X
H
X
X
L
H
logic symbol^†
1
1A
&
2
1B
13
1C
3
2A
4
2B
5
2C
9
3A
10
3B
11
3C
12
1Y
6
2Y
8
3Y
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.}
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1