SN74ALVC00_07 Datasheet, PDF (1/16 Pages) Texas Instruments – QUADRUPLE 2-INPUT POSITIVE-NAND GATE

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FEATURES
• Operates From 1.65 V to 3.6 V
• Max t_pd of 3 ns at 3.3 V
• ±24-mA Output Drive at 3.3 V
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
D, DGV, NS, OR PW PACKAGE
(TOP VIEW)
SN74ALVC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
SCES115G – JULY 1997 – REVISED AUGUST 2004
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
RGY PACKAGE
(TOP VIEW)
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 V_CC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
1
1B 2
1Y 3
2A 4
2B 5
2Y 6
7
14
13 4B
12 4A
11 4Y
10 3B
9 3A
8
DESCRIPTION/ORDERING INFORMATION
This quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V V_CC operation.
The SN74ALVC00 performs the Boolean function Y = A · B or Y = A + B in positive logic.
T_A
-40°C to 85°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
QFN - RGY
Tape and reel
SN74ALVC00RGYR
SOIC - D
Tube
Tape and reel
SN74ALVC00D
SN74ALVC00DR
SOP - NS
Tape and reel
SN74ALVC00NSR
TSSOP - PW
Tape and reel
SN74ALVC00PWR
TVSOP - DGV
Tape and reel
SN74ALVC00DGVR
TOP-SIDE MARKING
VA00
ALVC00
ALVC00
VA00
VA00
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
A
B
H
H
L
X
X
L
OUTPUT
Y
L
H
H
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
A
Y
B
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2004, Texas Instruments Incorporated