SN74ALVC00 Datasheet, PDF (1/7 Pages) Texas Instruments – QUADRUPLE 2-INPUT POSITIVE-NAND GATE

SN74ALVC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
D EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages
SCES115C – JULY 1997 – REVISED AUGUST 1998
D, DGV, OR PW PACKAGE
(TOP VIEW)
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 V_CC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
description
This quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V V_CC operation.
The SN74ALVC00 performs the Boolean function Y = A • B or Y = A + B in positive logic.
The SN74ALVC00 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
A
B
OUTPUT
Y
H
H
L
L
X
H
X
L
H
logic symbol^†
1
1A
&
3
2
1Y
1B
4
2A
5
2B
6
2Y
9
3A
10
3B
8
3Y
12
4A
13
4B
11
4Y
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.}
logic diagram, each gate (positive logic)
A
Y
B
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
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