SN74ACT7803 Datasheet, PDF (1/16 Pages) Texas Instruments – 512 ®18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SN74ACT7803
512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS191C – MARCH 1991 – REVISED APRIL 1998
D Member of the Texas Instruments
Widebus™ Family
DL PACKAGE
(TOP VIEW)
D Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident
D Read and Write Operations Synchronized
to Independent System Clocks
D Input-Ready Flag Synchronized to Write
RESET 1
D17 2
D16 3
D15 4
D14 5
56 OE1
55 Q17
54 Q16
53 Q15
52 GND
Clock
D Output-Ready Flag Synchronized to Read
Clock
D13 6
D12 7
D11 8
51 Q14
50 V_CC
49 Q13
D 512 Words by 18 Bits
D Low-Power Advanced CMOS Technology
D Half-Full Flag and Programmable
Almost-Full/Almost-Empty Flag
D Bidirectional Configuration and Width
Expansion Without Additional Logic
D Fast Access Times of 12 ns With a 50-pF
D10 9
V_CC 10
D9 11
D8 12
GND 13
D7 14
D6 15
D5 16
48 Q12
47 Q11
46 Q10
45 Q9
44 GND
43 Q8
42 Q7
41 Q6
Load and All Data Outputs Switching
D4 17 40 Q5
Simultaneously
D Data Rates up to 67 MHz
D Pin-to-Pin Compatible With SN74ACT7805
and SN74ACT7813
D Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Spacing
D3 18
D2 19
D1 20
D0 21
HF 22
PEN 23
AF/AE 24
WRTCLK 25
39 V_CC
38 Q4
37 Q3
36 Q2
35 GND
34 Q1
33 Q0
32 RDCLK
description
WRTEN2 26
WRTEN1 27
31 RDEN
30 OE2
The SN74ACT7803 is a 512-word × 18-bit FIFO
IR 28 29 OR
suited for buffering asynchronous datapaths up to
67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering
without additional logic. Multiple distributed V_CC and GND pins, along with Texas Instruments patented output
edge control (OEC™) circuit, dampen simultaneous switching noise.
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.
Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input
ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low
and output ready (OR) is high. The first word written to memory is clocked through to the output buffer,
regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output
buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four
WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes
the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be
reset upon power up.
The SN74ACT7803 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and OEC are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
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