SN74ACT72211L15RJ Datasheet, PDF (1/21 Pages) Texas Instruments – SYNCHRONOUS FIRST-IN FIRST-OUT MEMORIES

SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 × 9, 1024 × 9, 2048 × 9, AND 4096 × 9
SYNCHRONOUS FIRSTĆIN, FIRSTĆOUT MEMORIES
SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
D Read and Write Clocks Can Be
Asynchronous or Coincident
D Organization:
− SN74ACT72211L − 512 × 9
− SN74ACT72221L − 1024 × 9
− SN74ACT72231L − 2048 × 9
− SN74ACT72241L − 4096 × 9
D Write and Read Cycle Times of 15 ns
D Bit-Width Expandable
D Empty and Full Flags
D Programmable Almost-Empty and
Almost-Full Flags With Default Offsets
of Empty+7 and Full −7, Respectively
D TTL-Compatible Inputs
D Fully Compatible With the
IDT72211 / 72221/ 72231/ 72241
D Available in 32-Pin Plastic J-Leaded
Chip Carrier (RJ)
RJ PACKAGE
(TOP VIEW)
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
RS
WEN1
WCLK
WEN2/LD
V_CC
Q8
Q7
Q6
Q5
description
The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are constructed with
CMOS dual-port SRAM and are arranged as 512, 1024, 2048, and 4096 9-bit words, respectively. Internal write
and read address counters provide data throughput on a first-in, first-out (FIFO) basis. Full and empty flags
prevent memory overflow and underflow, and two programmable flags (almost full and almost empty) are
provided.
The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are synchronous FIFOs,
which means the data input port and data output port each employ synchronous control. Write-enable (WEN1,
WEN2/LD) signals allow the low-to-high transition of the write clock (WCLK) to store data in memory, and
read-enable (REN1, REN2) signals allow the low-to-high transition of the read clock (RCLK) to read data from
memory. WCLK and RCLK are independent of one another and can operate asynchronously or be tied together
for single-clock operation.
The empty-flag (EF) output is synchronized to RCLK and the full-flag (FF) output is synchronized to WCLK to
indicate absolute boundary conditions. Write operations are prohibited when FF is low, and read operations are
prohibited when EF is low. Two programmable flags, programmable almost empty (PAE) and programmable
almost full (PAF), can both be programmed to indicate any measure of memory fill. After reset, PAE defaults
to empty +7 and PAF defaults to full −7. Flag-offset programming control is similar to a memory write with the
use of the load (WEN2/LD) signal.
These devices are suited for providing a data channel between two buses operating at asynchronous or
synchronous rates. Applications include use as rate buffers for graphics systems and high-speed queues for
communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus a parity bit
or packet-framing information.
The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are characterized for
operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1993, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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