SN74ACT7200L Datasheet, PDF (1/23 Pages) Texas Instruments – 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
D Reads and Writes Can Be Asynchronous
or Coincident
D Organization:
– SN74ACT7200L – 256 × 9
– SN74ACT7201LA – 512 × 9
– SN74ACT7202LA – 1024 × 9
D Fast Data Access Times of 15 ns
D Read and Write Frequencies up to 40 MHz
D Bit-Width and Word-Depth Expansion
D Fully Compatible With the
IDT7200/ 7201 / 7202
D Retransmit Capability
D Empty, Full, and Half-Full Flags
D TTL-Compatible Inputs
D Available in 28-Pin Plastic DIP (NP),
Small-Outline (DV), and 32-Pin Plastic
J-Leaded Chip-Carrier (RJ) Packages
description
DV OR NP PACKAGE
(TOP VIEW)
W1
D8 2
D3 3
D2 4
D1 5
D0 6
XI 7
FF 8
Q0 9
Q1 10
Q2 11
Q3 12
Q8 13
GND 14
28 V_CC
27 D4
26 D5
25 D6
24 D7
23 FL /RT
22 RS
21 EF
20 XO/HF
19 Q7
18 Q6
17 Q5
16 Q4
15 R
RJ PACKAGE
(TOP VIEW)
The SN74ACT7200L, SN74ACT7201LA, and
SN74ACT7202LA are constructed with dual-port
SRAM and have internal write and read address
counters to provide data throughput on a first-in,
first-out (FIFO) basis. Write and read operations
are independent and can be asynchronous or
coincident. Empty and full status flags prevent
underflow and overflow of memory, and
depth-expansion logic allows combining the
storage cells of two or more devices into one
FIFO. Word-width expansion is also possible.
Data is loaded into memory by the write-enable
(W) input and unloaded by the read-enable (R)
input. Read and write cycle times of 25 ns
(40 MHz) are possible with data access times of
15 ns.
4 3 2 1 32 31 30
D2 5
29 D6
D1 6
28 D7
D0 7
27 NC
XI 8
26 FL /RT
FF 9
25 RS
Q0 10
24 EF
Q1 11
23 XO/HF
NC 12
22 Q7
Q2 13
21 Q6
14 15 16 17 18 19 20
NC – No internal connection
These devices are particularly suited for providing a data channel between two buses operating at
asynchronous rates. Applications include use as rate buffers from analog-to-digital converters in data-
acquisition systems, temporary storage elements between buses and magnetic or optical memories, and
queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus
a parity bit or packet-framing information. The read pointer can be reset independently of the write pointer for
retransmitting previously read data when a device is not used in depth expansion.
The SN74ACT7200L, SN74ACT7201LA, and SN74ACT7202LA are characterized for operation from 0°C
to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1995, Texas Instruments Incorporated
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