SN74ACT2227 Datasheet, PDF (1/13 Pages) Texas Instruments – DUAL 64 × 1, DUAL 256 × 1 FIRST-IN, FIRST-OUT MEMORIES

D Dual Independent FIFOs Organized as:
64 Words by 1 Bit Each – SN74ACT2227
256 Words by 1 Bit Each – SN74ACT2229
D Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident on Each
FIFO
D Input-Ready Flags Synchronized to Write
Clocks
D Output-Ready Flags Synchronized to Read
Clocks
D Half-Full and Almost-Full/Almost-Empty
Flags
D Support Clock Frequencies up to 60 MHz
D Access Times of 9 ns
D 3-State Data Outputs
D Low-Power Advanced CMOS Technology
D Packaged in 28-Pin SOIC Package
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
DW PACKAGE
(TOP VIEW)
1HF 1
1AF/AE 2
1WRTCLK 3
1WRTEN 4
1IR 5
1D 6
GND 7
GND 8
1RESET 9
2Q 10
2OR 11
2RDEN 12
2RDCLK 13
2OE 14
28 1OE
27 1RDCLK
26 1RDEN
25 1OR
24 1Q
23 2RESET
22 V_CC
21 V_CC
20 2D
19 2IR
18 2WRTEN
17 2WRTCLK
16 2AF/AE
15 2HF
description
The SN74ACT2227 and SN74ACT2229 are dual FIFOs suited for a wide range of serial-data buffering
applications including elastic stores for frequencies up to OC-1 telecommunication rates. Each FIFO on the chip
is arranged as 64 × 1 (SN74ACT2227) or 256 × 1 (SN74ACT2229) and has control signals and status flags for
independent operation. Output flags for each FIFO include input ready (1IR or 2IR), output ready (1OR or 2OR),
half full (1HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE).
Serial data is written into a FIFO on the low-to-high transition of the write-clock (1WRTCLK or 2WRTCLK) input
when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR) output are both high.
Serial data is read from a FIFO on the low-to-high transition of the read-clock (1RDCLK or 2RDCLK) input when
the read-enable (1RDEN or 2RDEN) input and output-ready flag (1OR or 2OR) output are both high. The read
and write clocks of a FIFO can be asynchronous to one another. A FIFO data output (1Q or 2Q) is in the
high-impedance state when its output-enable (1OE or 2OE) input is low.
Each input-ready flag (1IR or 2IR) is synchronized by two flip-flop stages to its write clock (1WRTCLK or
2WRTCLK), and each output-ready flag (1OR or 2OR) is synchronized by three flip-flop stages to its read clock
(1RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written
and read asynchronously.
A half-full flag (1HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half
the depth of the FIFO. An almost-full/almost-empty flag (1AF/AE or 2AF/AE) is high when eight or fewer bits
are stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data
output is not stored in the FIFO.
The SN74ACT2227 and SN74ACT2229 are characterized for operation from – 40°C to 85°C.
For more information on this device family, see the application report FIFOs With a Word Width of One Bit
(literature number SCAA006).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1997, Texas Instruments Incorporated
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