SN74AC533PWR Datasheet, PDF (1/11 Pages) Texas Instruments – OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54AC533, SN74AC533
OCTAL TRANSPARENT DĆTYPE LATCHES
WITH 3ĆSTATE OUTPUTS
SCAS555C − NOVEMBER 1995 − REVISED OCTOBER 2003
D 2-V to 6-V V_CC Operation
D Inputs Accept Voltages to 6 V
D Max t_pd of 10.5 ns at 5 V
D 3-State Inverting Outputs Drive Bus Lines
Directly
D Full Parallel Access for Loading
description/ordering information
The ’AC533 devices are octal transparent D-type
latches with 3-state outputs. When the
latch-enable (LE) input is high, the Q outputs
follow the complements of the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the inverse logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
OE does not affect the internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
SN54AC533 . . . J OR W PACKAGE
SN74AC533 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
OE ¹
1Q ²
1D ³
2D ⁴
2Q ⁵
3Q ⁶
3D ⁷
4D ⁸
4Q ⁹
GND ¹⁰
20 _VCC
19 _8Q
18 _8D
17 _7D
16 _7Q
15 _6Q
14 _6D
13 _5D
12 _5Q
11 _LE
SN54AC533 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
2D 4
18 8D
2Q 5
17 7D
3Q 6
16 7Q
3D 7
15 6Q
4D 8
14 6D
9 10 11 12 13
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube
SN74AC533N
SN74AC533N
SOIC − DW
Tube
Tape and reel
SN74AC533DW
SN74AC533DWR
AC533
−40°C to 85°C
SOP − NS
SSOP − DB
Tape and reel
Tape and reel
SN74AC533NSR
SN74AC533DBR
AC533
AC533
TSSOP − PW
Tube
Tape and reel
SN74AC533PW
SN74AC533PWR
AC533
CDIP − J
Tube
SNJ54AC533J
SNJ54AC533J
−55°C to 125°C CFP − W
Tube
SNJ54AC533W
SNJ54AC533W
LCCC − FK
Tube
SNJ54AC533FK
SNJ54AC533FK
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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