SN74ABT3611 Datasheet, PDF (1/26 Pages) Texas Instruments – 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

D Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
D 64 × 36 Clocked FIFO Buffering Data From
Port A to Port B
D Mailbox-Bypass Register In Each Direction
D Programmable Almost-Full and
Almost-Empty Flags
D Microprocessor Interface Control Logic
D Full Flag and Almost-Full Flag
Synchronized by CLKA
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
D Empty Flag and Almost-Empty Flag
Synchronized by CLKB
D Passive Parity Checking on Each Port
D Parity Generation Can Be Selected for Each
Port
D Low-Power Advanced BiCMOS Technology
D Supports Clock Frequencies up to 67 MHz
D Fast Access Times of 10 ns
D Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages
description
The SN74ABT3611 is a high-speed, low-power BiCMOS clocked FIFO memory. It supports clock frequencies
up to 67 MHz and has read access times as fast as 10 ns. A 64 × 36 dual-port SRAM FIFO buffers data from
port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost
full and almost empty) to indicate when a selected number of words is stored in memory. Communication
between each port takes place through two 36-bit mailbox registers. Each mailbox register has a flag to signal
when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired.
Parity generation can be selected for data read from each port. Two or more devices are used in parallel to create
wider datapaths.
The SN74ABT3611 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port
are arranged to provide a simple bidirectional interface between microprocessors and/or buses with
synchronous control.
The full flag (FF) and almost-full (AF) flag of the FIFO are two-stage synchronized to the port clock that writes
data to its array (CLKA). The empty flag (EF) and almost-empty (AE) flag of the FIFO are two-stage
synchronized to the port clock that reads data from its array.
The SN74ABT3611 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the following application reports:
• FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature
number SCAA007)
• Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications
(literature number SCAA015)
• Metastability Performance of Clocked FIFOs (literature number SCZA004)
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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