SN65MLVD080_07 Datasheet, PDF (1/28 Pages) Texas Instruments – 8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS

www.ti.com
SN65MLVD080
SN65MLVD082
SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS
FEATURES
• Low-Voltage Differential 30-Ω to 55-Ω Line
Drivers and Receivers for Signaling Rates ⁽¹⁾
Up to 250 Mbps; Clock Frequencies Up to
125 MHz
• Meets or Exceeds the M-LVDS Standard
TIA/EIA-899 for Multipoint Data Interchange
• Controlled Driver Output Voltage Transition
Times for Improved Signal Quality
• –1 V to 3.4 V Common-Mode Voltage Range
Allows Data Transfer With 2 V of Ground
Noise
• Bus Pins High Impedance When Driver
Disabled or V_CC ≤ 1.5 V
• Independent Enables for each Driver
• Bus Pin ESD Protection Exceeds 8 kV
• Packaged in 64-Pin TSSOP (DGG)
• M-LVDS Bus Power Up/Down Glitch Free
APPLICATIONS
• Parallel Multipoint Data and Clock
Transmission Via Backplanes and Cables
• Low-Power High-Speed Short-Reach
Alternative to TIA/EIA-485
• Cellular Base Stations
• Central-Office Switches
• Network Switches and Routers
DESCRIPTION
The SN65MLVD080 and SN65MLVD082 provide
eight half-duplex transceivers for transmitting and
receiving Multipoint-Low-Voltage Differential Signals
in full compliance with the TIA/EIA-899 (M-LVDS)
standard, which are optimized to operate at signaling
rates up to 250 Mbps. The driver outputs have been
designed to support multipoint buses presenting
loads as low as 30-Ω and incorporates controlled
transition times to allow for stubs off of the backbone
transmission line.
(1) The signaling rate of a line, is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
The M-LVDS standard defines two types of receivers,
designated as Type-1 and Type-2. Type-1 receivers
(SN65MLVD080) have thresholds centered about
zero with 25 mV of hysteresis to prevent output
oscillations with loss of input; Type-2 receivers
(SN65MLVD082) implement a failsafe by using an
offset threshold. In addition, the driver rise and fall
times are between 1 and 2.0 ns, complying with the
M-LVDS standard to provide operation at 250 Mbps
while also accommodating stubs on the bus. Receiver
outputs are slew rate controlled to reduce EMI and
crosstalk effects associated with large current surges.
The M-LVDS standard allows for 32 nodes on the bus
providing a high-speed replacement for RS-485
where lower common-mode can be tolerated or when
higher signaling rates are needed.
The driver logic inputs and the receiver logic outputs
are on separate pins rather than tied together as in
some transceiver designs. The drivers have separate
enables (DE) and the receivers are enabled globally
through (RE). This arrangement of separate logic
inputs, logic outputs, and enable pins allows for a
listen-while-talking operation. The devices are
characterized for operation from –40°C to 85°C.
LOGIC DIAGRAM (POSITIVE LOGIC)
SN65MLVD080, SN65MLVD082
Channel 1
1DE
1A
1D
1B
1R
RE
7
2DE - 8DE
2D - 8D ⁷
2R - 8R ⁷
Channels 2 - 8
2A - 8A
2B - 8B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated