SN65LVEP11_10 Datasheet, PDF (1/12 Pages) Texas Instruments – 2.5 V/3.3 V PECL/ECL 1:2 Fanout Buffer

SN65LVEP11
www.ti.com ........................................................................................................................................ SLLS930A – NOVEMBER 2008 – REVISED DECEMBER 2008
2.5 V/3.3 V PECL/ECL 1:2 Fanout Buffer
FEATURES
1
• 1:2 PECL/ECL Fanout Buffer
• Operating Range
PINOUT ASSIGNMENT
– PECL: V_CC = 2.375 V to 3.8V With V_EE = 0 V
– NECL: V_CC = 0 V With V_EE = –2.375V to
–3.8 V
Q₀ 1
+
8 V_CC
• Open Input Default State
• Support for Clock Frequencies > 3.0 GHz
• 240 ps Typical Propagation Delay
• Deterministic Output Value for Open Input
Conditions
Q₀ 2
Q₁ 3
7D
+
6D
• Q Output Will Default Low When Input Open or
at V_EE
• Built-in Temperature Compensation
• Drop in Compatible to MC10LVEP11,
MC100LVEP11
PIN
Q₁ 4
5 V_EE
Table 1. PIN DESCRIPTION
FUNCTION
• LVDS Input Compatible
D, D
PECL/ECL data inputs
DESCRIPTION
Q₀, Q₀, Q₁, Q₁
V_CC
PECL/ECL outputs
Positive supply
The SN65LVEP11 is a differential 1:2 PECL/ECL
V_EE
fanout buffer. The device includes circuitry to
maintain known logic levels when the inputs are in an
open condition. Single-ended clock input operation is
limited to V_CC ≥ 3 V in PECL mode, or V_EE ≤ 3 V in
NECL mode. The device is housed in an
industry-standard SOIC-8 package and is also
available in TSSOP-8 package option.
ORDERING INFORMATION⁽¹⁾
Negative supply
PART NUMBER
SN65LVEP11D
SN65LVEP11DGK
PART MARKING
SN65LVEP11
SN65LVEP11
PACKAGE
SOIC
SOIC-TSSOP
LEAD FINISH
NiPdAu
NiPdAu
(1) Leaded device option not initially available; contact TI sales representative for further information.
1
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated