SN65LVDT100D Datasheet, PDF (1/25 Pages) Texas Instruments – DIFFERENTIAL TRANSLATOR/REPEATER

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SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
DIFFERENTIAL TRANSLATOR/REPEATER
FEATURES
• Designed for Signaling Rates ⁽¹⁾ ≥ 2 Gbps
• Total Jitter < 65 ps
• Low-Power Alternative for the MC100EP16
• Low 100 ps (Max) Part-To-Part Skew
• 25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Common-Mode Range
• Inputs Electrically Compatible With LVPECL,
CML, and LVDS Signal Levels
• 3.3-V Supply Operation
• LVDT Integrates 110-Ω Terminating Resistor
• Offered in SOIC and MSOP
APPLICATIONS
• 622 MHz Central Office Clock Distribution
• High-Speed Network Routing
• Wireless Basestations
• Low Jitter Clock Repeater
• Serdes LVPECL Output to FPGA LVDS
Input Translator
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
DESCRIPTION
The SN65LVDS100, SN65LVDT100, SN65LVDS101,
and SN65LVDT101 are a high-speed differential re-
ceiver and driver connected as a repeater. The
receiver accepts low-voltage differential signaling
(LVDS), positive-emitter-coupled logic (PECL), or cur-
rent-mode logic (CML) input signals at rates up to 2
Gbps and repeats it as either an LVDS or PECL
output signal. The signal path through the device is
differential for low radiated emissions and minimal
added jitter.
The outputs of the SN65LVDS100 and
SN65LVDT100 are LVDS levels as defined by
TIA/EIA-644-A. The outputs of the SN65LVDS101
and SN65LVDT101 are compatible with 3.3-V PECL
levels. Both drive differential transmission lines with
nominally 100-Ω characteristic impedance.
The SN65LVDT100 and SN65LVDT101 include a
110-Ω differential line termination resistor for less
board space, fewer components, and the shortest
stub length possible. They do not include the V_BB
voltage reference found in the SN65LVDS100 and
SN65LVDS101. V_BB provides a voltage reference of
typically 1.35 V below V_CC for use in receiving
single-ended input signals and is particularly useful
with single-ended 3.3-V PECL inputs. When not used,
V_BB should be unconnected or open.
All devices are characterized for operation from
–40°C to 85°C.
FUNCTIONAL DIAGRAM
EYE PATTERN
SN65LVDS100 and SN65LVDS101
V_CC ⁸
4
2
A
7
6
B3
V_BB
2 Gbps
2²³ - 1 PRBS
Y
V_CC = 3.3 V
Z
V_ID = 200 mV
V_IC = 1.2 V
Vert.Scale= 200 mV/div
SN65LVDT100 and SN65LVDT101
2
A
110 Ω
B3
7
Y
6Z
1 GHz
Horizontal Scale= 200 ps/div
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRO-
DUCTION DATA information current as of publication date. Prod-
ucts conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
Copyright © 2002–2004, Texas Instruments Incorporated