SN65LVDS95DGGR Datasheet, PDF (1/18 Pages) Texas Instruments – LVDS SERDES TRANSMITTER

SN65LVDS95
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LVDS SERDES TRANSMITTER
Check for Samples: SN65LVDS95
SLLS297J – MAY 1998 – REVISED MAY 2011
FEATURES
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• 3:21 Data Channel Compression at up to
1.428 Gigabits/s Throughput
• Suited for Point-to-Point Subsystem
Communication With Very Low EMI
• 21 Data Channels Plus Clock in Low-Voltage
TTL and 3 Data Channels Plus Clock Out
Low-Voltage Differential
• Operates From a Single 3.3-V Supply and
250 mW (Typ)
• 5-V Tolerant Data Inputs
• 'LVDS95 Has Rising Clock Edge Triggered
Inputs
• Bus Pins Tolerate 6-kV HBM ESD
• Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
• Consumes <1 mW When Disabled
• Wide Phase-Lock Input Frequency Range
20 MHz to 68 MHz
• No External Components Required for PLL
• Inputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
• Industrial Temperature Qualified
T_A = –40°C to 85°C
• Replacement for the National DS90CR215
DGG PACKAGE
(TOP VIEW)
D4 1
V_CC 2
D5 3
D6 4
GND 5
D7 6
D8 7
V_CC 8
D9 9
D10 10
GND 11
D11 12
D12 13
NC 14
D13 15
D14 16
GND 17
D15 18
D16 19
D17 ²⁰
V_CC ²¹
D18 ²²
D19 ²³
GND ²⁴
48 D3
47 D2
46 GND
45 D1
44 D0
43 NC
42 LVDSGND
41 Y0M
40 Y0P
39 Y1M
38 Y1P
37 LVDSV_CC
36 LVDSGND
35 Y2M
34 Y2P
33 CLKOUTM
32 CLKOUTP
31 LVDSGND
30 PLLGND
29 _PLLVCC
28 _PLLGND
27 _SHTDN
26 _CLKIN
25 _D20
DESCRIPTION
The SN65LVDS95 LVDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out
shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single
integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over
4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96.
When transmitting, data bits D0 through D20 are each loaded into registers of the SN65LVDS95 on the rising
edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to
serially unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT)
are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN65LVDS95 requires no external components and little or no control. The data bus appears the same at
the input to the transmitter and output of the receiver with data transmission transparent to the user(s). The only
user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut
off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to
a low level.
The SN65LVDS95 is characterized for operation over ambient air temperatures of –40°C to 85°C.
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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