SN65LVDS94DGGG4 Datasheet, PDF (1/17 Pages) Texas Instruments – LVDS SERDES RECEIVER

SN65LVDS94
www.ti.com
SLLS298F – MAY 1998 – REVISED JANUARY 2006
LVDS SERDES RECEIVER
FEATURES
• 4:28 Data Channel Expansion at up to 1.904
Gigabits per Second Throughput
• Suited for Point-to-Point Subsystem
Communication With Very Low EMI
• 4 Data Channels and Clock Low-Voltage
Differential Channels in and 28 Data and
Clock Out Low-Voltage TTL Channels Out
• Operates From a Single 3.3-V Supply and
250 mW (Typ)
• 5-V Tolerant SHTDN Input
• Rising Clock Edge Triggered Outputs
• Bus Pins Tolerate 4-kV HBM ESD
• Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
• Consumes <1 mW When Disabled
• Wide Phase-Lock Input Frequency Range
20 MHz to 68 MHz
• No External Components Required for PLL
• Meets or Exceeds the Requirements of ANSI
EIA/TIA-644 Standard
• Industrial Temperature Qualified
T_A = -40°C to 85°C
• Replacement for the DS90CR286
DGG PACKAGE
(TOP VIEW)
D22 ₁
D23 2
D24 3
GND 4
D25 5
D26 6
D27 7
LVDSGND 8
A0M 9
A0P 10
A1M 11
A1P 12
LVDSV_CC 13
LVDSGND 14
A2M 15
A2P 16
CLKINM 17
CLKINP 18
A3M 19
A3P 20
LVDSGND 21
PLLGND 22
PLLV_CC ²³
PLLGND ²⁴
SHTDN ²⁵
CLKOUT ²⁶
D0 ²⁷
GND ²⁸
56 ^VCC
55 D21
54 D20
53 D19
52 GND
51 D18
50 D17
49 D16
48 V_CC
47 D15
46 D14
45 D13
44 GND
43 D12
42 D11
41 D10
40 V_CC
39 D9
38 D8
37 D7
36 GND
35 D6
34 _D5
33 _D4
32 _D3
31 _VCC
30 _D2
29 _D1
DESCRIPTION
The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift
registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single
integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the
SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended
LVTTL synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the
LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A
phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the
expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2006, Texas Instruments Incorporated