SN65LVDS94 Datasheet, PDF (1/14 Pages) Texas Instruments – LVDS SERDES RECEIVER

SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
D 4:28 Data Channel Expansion at up to
1.820 Gigabits per Second Throughput
DGG PACKAGE
(TOP VIEW)
D Suited for Point-to-Point Subsystem
Communication With Very Low EMI
D 4 Data Channels and Clock Low-Voltage
Differential Channels in and 28 Data and
Clock Out Low-Voltage TTL Channels Out
D Operates From a Single 3.3-V Supply and
250 mW (Typ)
D 5-V Tolerant SHTDN Input
D22 ₁
D23 ₂
D24 3
GND 4
D25 5
D26 6
D27 7
LVDSGND 8
56 ^V_CC
55 ^D21
54 D20
53 D19
52 GND
51 D18
50 D17
49 D16
D Rising Clock Edge Triggered Outputs
D Bus Pins Tolerate 4-kV HBM ESD
D Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
D Consumes <1 mW When Disabled
D Wide Phase-Lock Input Frequency Range
A0M 9
A0P 10
A1M 11
A1P 12
LVDSV_CC 13
LVDSGND 14
A2M 15
48 V_CC
47 D15
46 D14
45 D13
44 GND
43 D12
42 D11
20 MHz to 65 MHz
A2P 16 41 D10
D No External Components Required for PLL
CLKINM 17 40 V_CC
D Meets or Exceeds the Requirements of
ANSI EIA/TIA-644 Standard
D Industrial Temperature Qualified
T_A = – 40°C to 85°C
D Replacement for the DS90CR286
description
CLKINP 18
A3M 19
A3P 20
LVDSGND 21
PLLGND 22
PLLV_CC ²³
PLLGND ²⁴
SHTDN ²⁵
39 D9
38 D8
37 D7
36 GND
35 D6
34 _D5
33 _D4
32 _D3
The SN65LVDS94 LVDS serdes (serializer/des-
erializer) receiver contains four serial-in 7-bit
parallel-out shift registers, a 7× clock synthesizer,
CLKOUT ²⁶
D0 ²⁷
GND ²⁸
31 _VCC
30 _D2
29 _D1
and five low-voltage differential signaling (LVDS)
line receivers in a single integrated circuit. These
functions allow receipt of synchronous data from
a compatible transmitter, such as the SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and
expansion to 28 bits of single-ended LVTTL synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the
LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A
phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for
the expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).
The SN65LVDS94 requires only five line termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear
(SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A
low level on this signal clears all internal registers to a low level.
The SN65LVDS94 is characterized for operation over ambient air temperatures of – 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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