SN65LVDS93A Datasheet, PDF (1/25 Pages) Texas Instruments – FLATLINK TRANSMITTER

SN65LVDS93A
www.ti.com................................................................................................................................................................................................. SLLS992 – AUGUST 2009
FLATLINK™ TRANSMITTER
Check for Samples: SN65LVDS93A
FEATURES
1
•2 Industrial Temperature Range –40°C to 85°C
• LVDS Display Serdes Interfaces Directly to
LCD Display Panels with Integrated LVDS
• Package Options: 4.5mm × 7mm BGA, and
8.1mm × 14mm TSSOP
• 1.8V up to 3.3V Tolerant Data Inputs to
Connect Directly to Low-Power, Low-Voltage
Application and Graphic Processors
• Transfer Rate up to 135Mpps (Mega Pixel Per
Second); Pixel Clock Frequency Range 10MHz
to 135MHz
• Suited for Display Resolutions Ranging From
HVGA up to HD With Low EMI
• Operates From a Single 3.3V Supply and
170mW (typ.) at 75MHz
• 28 Data Channels Plus Clock In Low-Voltage
TTL to 4 Data Channels Plus Clock Out
Low-Voltage Differential
• Consumes Less Than 1mW When Disabled
• Selectable Rising or Falling Clock Edge
Triggered Inputs
• ESD: 5kV HBM
• Support Spread Spectrum Clocking (SSC)
• Compatible with all OMAP ™ 2x, OMAP™3x,
and DaVinci ™ Application Processors
APPLICATIONS
• LCD Display Panel Driver
• UMPC and Netbook PC
• Digital Picture Frame
DESCRIPTION
The SN65LVDS93A LVDS serdes (serializer/deserializer) transmitter contains four 7-bit parallel load serial-out
shift registers, a 7 × clock synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single
integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over
five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock
signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The
frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices.
The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The
frequency of CLKOUT is the same as the input clock, CLKIN.
The SN65LVDS93A requires no external components and little or no control. The data bus appears the same at
the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The
only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a
lowlevel input and the possible use of the shutdown/clear (SHTDN). SHTDN is an active-low input to inhibit the
clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all
internal registers at a low level.
The SN65LVDS93A is characterized for operation over ambient air temperatures of –40°C to 85°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OMAP, DaVinci are trademarks of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated