SN65LVDS93 Datasheet, PDF (1/14 Pages) Texas Instruments – LVDS SERDES TRANSMITTER

SN65LVDS93
LVDS SERDES TRANSMITTER
SLLS302F – MAY 1998 – REVISED FEBRUARY 2000
D 28:4 Data Channel Compression at up to
1.82 Gigabits per Second Throughput
DGG PACKAGE
(TOP VIEW)
D Suited for Point-to-Point Subsystem
Communication With Very Low EMI
D 28 Data Channels Plus Clock in
Low-Voltage TTL and 4 Data Channels Plus
Clock Out Low-Voltage Differential
D Selectable Rising or Falling Clock Edge
Triggered Inputs
D Bus Pins Tolerate 6-kV HBM ESD
V_{CC 1}
D5 ₂
D6 3
D7 4
GND 5
D8 6
D9 7
D10 8
56 ^D4
55 ^D3
54 D2
53 GND
52 D1
51 D0
50 D27
49 LVDSGND
D Operates From a Single 3.3-V Supply and
250 mW (Typ)
D 5-V Tolerant Data Inputs
D Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
D Consumes <1 mW When Disabled
D Wide Phase-Lock Input Frequency Range
V_CC 9
D11 10
D12 11
D13 12
GND 13
D14 14
D15 15
D16 16
48 Y1M
47 Y1P
46 Y2M
45 Y2P
44 LVDSV_CC
43 LVDSGND
42 Y3M
41 Y3P
20 MHz to 65 MHz
CLKSEL 17 40 CLKOUTM
D No External Components Required for PLL
D17 18 39 CLKOUTP
D Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
D Industrial Temperature Qualified
T_A = – 40°C to 85°C
D Replacement for the DS90CR285
D18 19
D19 20
GND 21
D20 22
D21 ²³
D22 ²⁴
38 Y4M
37 Y4P
36 LVDSGND
35 PLLGND
34 _PLLVCC
33 _PLLGND
description
The SN65LVDS93 LVDS serdes (serializer/des-
erializer) transmitter contains four 7-bit parallel-
D23 ²⁵
V_CC ²⁶
D24 ²⁷
D25 ²⁸
32 _SHTDN
31 _CLKIN
30 _D26
29 _GND
load serial-out shift registers, a 7× clock
synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit. These
functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair
conductors for receipt by a compatible receiver, such as the SN65LVDS94.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock
signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The
frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices.
The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The
frequency of CLKOUT is the same as the input clock, CLKIN.
The SN65LVDS93 requires no external components and little or no control. The data bus appears the same
at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s).
The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge
with a low-level input and the possible use of the shutdown/clear (SHTDN). SHTDN is an active-low input to
inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal
clears all internal registers at a low level.
The SN65LVDS93 is characterized for operation over ambient air temperatures of – 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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