SN65LVDS388 Datasheet, PDF (1/14 Pages) Texas Instruments – HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
D Eight Line Receivers Meet or Exceed the
Requirements of ANSI TIA/EIA-644
Standard
D Integrated 110-Ω Line Termination
Resistors on LVDT Products
D Designed for Signaling Rates^† Up To
630 Mbps
D SN65 Version’s Bus-Terminal ESD Exceeds
15 kV
D Operates From a Single 3.3-V Supply
D Propagation Delay Time of 2.6 ns (Typ)
D Output Skew 100 ps (Typ)
Part-To-Part Skew Is Less Than 1 ns
D LVTTL Levels Are 5-V Tolerant
D Open-Circuit Fail Safe
D Flow-Through Pin Out
D Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
description
The ‘LVDS388 and ‘LVDT388 (T designates
integrated termination) are eight differential line
receivers that implement the electrical character-
istics of low-voltage differential signaling (LVDS).
This signaling technique lowers the output voltage
levels of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a 3-V
supply rail. Any of the eight differential receivers
will provide a valid logical output state with a
+100-mV differential input voltage within the input
common-mode voltage range. The input
common-mode voltage range allows 1 V of
ground potential difference between two LVDS
nodes. Additionally, the high-speed switching of
LVDS signals always require the use of a line
impedance matching resistor at the receiving end
of the cable or transmission media. The LVDT
product eliminates this external resistor by
integrating it with the receiver.
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
NOT RECOMMENDED FOR NEW DESIGNS
For Replacement Use ’LVDx388A
’LVDS388, ’LVDT388
DBT PACKAGE
(TOP VIEW)
A1A ¹
A1B ²
A2A ³
A2B ⁴
NC ⁵
B1A ⁶
B1B ⁷
B2A ⁸
B2B ⁹
NC ¹⁰
C1A ¹¹
C1B ¹²
C2A ¹³
C2B ¹⁴
NC ¹⁵
D1A ¹⁶
D1B ¹⁷
D2A ¹⁸
D2B 19
38 _GND
37 _VCC
36 _ENA
35 _A1Y
34 _A2Y
33 _ENB
32 _B1Y
31 _B2Y
30 _GND
29 _VCC
28 GND
27 C1Y
26 C2Y
25 ENC
24 D1Y
23 D2Y
22 END
21 V_CC
20 GND
logic diagram (positive logic)
’LVDx388
’LVDT388 ONLY
1A
1Y
1B
EN
2A
2Y
2B
(1/4 of ’LVDx388 shown)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† _{Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)}
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2001, Texas Instruments Incorporated
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