SN65LVDS387_07 Datasheet, PDF (1/18 Pages) Texas Instruments – HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
D Four (’391), Eight (’389) or Sixteen (’387)
Line Drivers Meet or Exceed the
Requirements of ANSI EIA / TIA-644
Standard
D Designed for Signaling Rates^† up to
630 Mbps With Very Low Radiation (EMI)
D Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100-Ω Load
D Propagation Delay Times Less Than 2.9 ns
D Output Skew Is Less Than 150 ps
D Part-to-Part Skew Is Less Than 1.5 ns
D 35-mW Total Power Dissipation in Each
Driver Operating at 200 MHz
D Driver Is High Impedance When Disabled or
With V_CC < 1.5 V
D SN65’ Version Bus-Pin ESD Protection
Exceeds 15 kV
D Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
D Low-Voltage TTL (LVTTL) Logic Inputs Are
5-V Tolerant
description
This family of four, eight, and sixteen differential
line drivers implements the electrical characteris-
tics of low-voltage differential signaling (LVDS).
This signaling technique lowers the output voltage
levels of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a
3.3-V supply rail. Any of the sixteen current-mode
drivers will deliver a minimum differential output
voltage magnitude of 247 mV into a 100-Ω load
when enabled.
’LVDS389
DBT PACKAGE
(TOP VIEW)
GND ₁
V_{CC 2}
GND ₃
ENA ₄
A1A ₅
A2A ₆
A3A ₇
A4A 8
GND 9
V_CC 10
GND 11
B1A 12
B2A 13
B3A 14
B4A 15
ENB 16
GND 17
V_CC 18
GND 19
38 ^A1Y
37 ^A1Z
36 ^A2Y
35 ^A2Z
34 ^A3Y
33 ^A3Z
32 ^A4Y
31 ^A4Z
30 ^NC
29 ^NC
28 ^NC
27 ^B1Y
26 ^B1Z
25 ^B2Y
24 B2Z
23 B3Y
22 B3Z
21 B4Y
20 B4Z
’LVDS391
D OR PW PACKAGE
(TOP VIEW)
EN1,2 1
1A 2
2A 3
V_CC 4
GND 5
3A 6
4A 7
EN3,4 8
16 1Y
15 1Z
14 2Y
13 2Z
12 3Y
11 3Z
10 4Y
9 4Z
’LVDS387
DGG PACKAGE
(TOP VIEW)
GND ₁
V_{CC 2}
V_{CC 3}
GND ₄
ENA ₅
A1A ₆
A2A ₇
A3A ₈
A4A ₉
ENB ₁₀
B1A ₁₁
B2A ₁₂
B3A ₁₃
B4A ₁₄
GND ₁₅
V_{CC 16}
V_{CC 17}
GND ₁₈
C1A ₁₉
C2A ₂₀
C3A ₂₁
C4A ₂₂
ENC 23
D1A 24
D2A 25
D3A 26
D4A 27
END 28
GND 29
V_CC 30
V_CC 31
GND 32
64 ^A1Y
63 ^A1Z
62 ^A2Y
61 ^A2Z
60 ^A3Y
59 ^A3Z
58 ^A4Y
57 ^A4Z
56 ^B1Y
55 ^B1Z
54 ^B2Y
53 ^B2Z
52 ^B3Y
51 ^B3Z
50 ^B4Y
49 ^B4Z
48 ^C1Y
47 ^C1Z
46 ^C2Y
45 ^C2Z
44 ^C3Y
43 ^C3Z
42 C4Y
41 C4Z
40 D1Y
39 D1Z
38 D2Y
37 D2Z
36 D3Y
35 D3Z
34 D4Y
33 D4Z
The intended application of this device and signaling technique is for point-to-point and multidrop baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media can be
printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same
substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of
clock and data for synchronous parallel data transfers. When used with the companion 16- or 8-channel
receivers, the SN65LVDS386 or SN65LVDS388, over 300 million data transfers per second in single-edge
clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† _{Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)}
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2001, Texas Instruments Incorporated
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