SN65LVDS386_08 Datasheet, PDF (1/25 Pages) Texas Instruments – HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394H – SEPTEMBER 1999 – REVISED MAY 2007
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
FEATURES
• Four- ('390), Eight- ('388A), or Sixteen- ('386)
Line Receivers Meet or Exceed the
Requirements of ANSI TIA/EIA-644 Standard
• Integrated 110-Ω Line Termination Resistors
on LVDT Products
• Designed for Signaling Rates ⁽¹⁾ Up To
200 Mbps (See Table 1)
• SN65 Version's Bus-Terminal ESD Exceeds
15 kV
• Operates From a Single 3.3-V Supply
• Typical Propagation Delay Time of 2.6 ns
• Output Skew 100 ps (Typ) Part-To-Part Skew
Is Less Than 1 ns
• LVTTL Levels Are 5-V Tolerant
• Open-Circuit Fail Safe
• Flow-Through Pinout
• Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
DESCRIPTION
This family of four-, eight-, or sixteen-, differential line
receivers (with optional integrated termination)
implements the electrical characteristics of
low-voltage differential signaling (LVDS). This
signaling technique lowers the output voltage levels
of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a 3-V
supply rail. Any of the eight or sixteen differential
receivers provides a valid logical output state with a
±100-mV differential input voltage within the input
common-mode voltage range. The input
common-mode voltage range allows 1 V of ground
potential difference between two LVDS nodes.
Additionally, the high-speed switching of LVDS
signals almost always requires the use of a line
impedance matching resistor at the receiving end of
the cable or transmission media. The LVDT products
eliminate this external resistor by integrating it with
the receiver.
(1) Signaling Rate, 1/t, where t is the minimum unit interval and is
expressed in the units bits/s (bits per second)
’LVDS388A, ’LVDT388A
DBT PACKAGE
(TOP VIEW)
A1A ¹
A1B ²
A2A ³
A2B ⁴
AGND ⁵
B1A ⁶
B1B ⁷
B2A ⁸
B2B ⁹
AGND ¹⁰
C1A ¹¹
C1B ¹²
C2A ¹³
C2B ¹⁴
AGND ¹⁵
D1A ¹⁶
D1B ¹⁷
D2A 18
D2B 19
38 _GND
37 _VCC
36 _ENA
35 _A1Y
34 _A2Y
33 _ENB
32 _B1Y
31 _B2Y
30 _DGND
29 _DVCC
28 DGND
27 C1Y
26 C2Y
25 ENC
24 D1Y
23 D2Y
22 END
21 V_CC
20 GND
See application section for V_CC
and GND description.
’LVDS390, ’LVDT390
D OR PW PACKAGE
(TOP VIEW)
1A 1
1B 2
2A 3
2B 4
3A 5
3B 6
4A 7
4B 8
16 EN1,2
15 1Y
14 2Y
13 V_CC
12 GND
11 3Y
10 4Y
9 EN3,4
’LVDS386, ’LVDT386
DGG PACKAGE
(TOP VIEW)
A1A 1
A1B 2
A2A 3
A2B 4
A3A 5
A3B 6
A4A 7
A4B 8
B1A 9
B1B 10
B2A 11
B2B 12
B3A 13
B3B 14
B4A 15
B4B 16
C1A 17
C1B 18
C2A 19
C2B 20
C3A 21
C3B 22
C4A 23
C4B 24
D1A 25
D1B 26
D2A 27
D2B 28
D3A 29
D3B ³⁰
D4A ³¹
D4B 32
64 GND
63 V_CC
62 V_CC
61 GND
60 ENA
59 A1Y
58 A2Y
57 A3Y
56 A4Y
55 ENB
54 B1Y
53 B2Y
52 B3Y
51 B4Y
50 GND
49 V_CC
48 V_CC
47 GND
46 C1Y
45 C2Y
44 C3Y
43 C4Y
42 ENC
41 D1Y
40 D2Y
39 D3Y
38 D4Y
37 END
36 GND
35 _VCC
34 _VCC
33 GND
Table 1. Maximum Recommeded Operating
Speeds
PART NUMBER
SN65LVDS386, SN75LVDS386
SN65LVDS388A, SN75LVDS388A
SN65LVDS390, SN75LVDS390
ALL BUFFERS ACTIVE
250 Mbps
200 Mbps
200 Mbps
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2007, Texas Instruments Incorporated