SN65LVDS386 Datasheet, PDF(1/15 Page) Texas Instruments – HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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SN65LVDS386 Datasheet, PDF (1/15 Pages) Texas Instruments – HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386

SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS394A â SEPTEMBER 1999 â REVISED DECEMBER 1999

D Eight (â388) or Sixteen (â386) Line Receivers

Meet or Exceed the Requirements of ANSI

TIA/EIA-644 Standard

D Integrated 110-â¦ Line Termination

Resistors on LVDT Products

D Designed for Signaling Ratesâ Up To

630 Mbps

D SN65 Versionâs Bus-Terminal ESD Exceeds

15 kV

D Operates From a Single 3.3-V Supply

D Typical Propagation Delay Time of 2.6 ns

D Output Skew 100 ps (Typ)

Part-To-Part Skew is Less Than 1 ns

D LVTTL Levels are 5-V Tolerant

D Open-Circuit Fail Safe

D Flow-Through Pin Out

D Packaged in Thin Shrink Small-Outline

Package With 20-mil Terminal Pitch

description

The âLVDS388 and âLVDT388 (T designates

integrated termination) are eight and the

âLVDS386 and âLVDT386 sixteen differential line

receivers respectively that implement the electri-

cal characteristics of low-voltage differential

signaling (LVDS). This signaling technique lowers

the output voltage levels of 5-V differential

standard levels (such as EIA/TIA-422B) to reduce

the power, increase the switching speeds, and

allow operation with a 3-V supply rail. Any of the

eight or sixteen differential receivers will provide

a valid logical output state with a Â±100 mV

differential input voltage within the input common-

mode voltage range. The input common-mode

voltage range allows 1 V of ground potential

difference between two LVDS nodes. Additionally,

the high-speed switching of LVDS signals almost

always require the use of a line impedance

matching resistor at the receiving end of the cable

or transmission media. The LVDT products

eliminate this external resistor by integrating it

with the receiver.

SN65LVDS388, SN75LVDS388

SN65LVDT388, SN75LVDT388

DBT PACKAGE

(TOP VIEW)

A1A 1

A1B 2

A2A 3

A2B 4

NC 5

B1A 6

B1B 7

B2A 8

B2B 9

NC 10

C1A 11

C1B 12

C2A 13

C2B 14

NC 15

D1A 16

D1B 17

D2A 18

D2B 19

38 GND

37 VCC

36 ENA

35 A1Y

34 A2Y

33 ENB

32 B1Y

31 B2Y

30 GND

29 VCC

28 GND

27 C1Y

26 C2Y

25 ENC

24 D1Y

23 D2Y

22 END

21 VCC

20 GND

SN65LVDS386, SN75LVDS386

SN65LVDT386, SN75LVDT386

DGG PACKAGE

(TOP VIEW)

A1A 1

A1B 2

A2A 3

A2B 4

A3A 5

A3B 6

A4A 7

A4B 8

B1A 9

B1B 10

B2A 11

B2B 12

B3A 13

B3B 14

B4A 15

B4B 16

C1A 17

C1B 18

C2A 19

C2B 20

C3A 21

C3B 22

C4A 23

C4B 24

D1A 25

D1B 26

D2A 27

D2B 28

D3A 29

D3B 30

D4A 31

D4B 32

64 GND

63 VCC

62 VCC

61 GND

60 ENA

59 A1Y

58 A2Y

57 A3Y

56 A4Y

55 ENB

54 B1Y

53 B2Y

52 B3Y

51 B4Y

50 GND

49 VCC

48 VCC

47 GND

46 C1Y

45 C2Y

44 C3Y

43 C4Y

42 ENC

41 D1Y

40 D2Y

39 D3Y

38 D4Y

37 END

36 GND

35 VCC

34 VCC

33 GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

â Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

â¢ POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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