SN65LVDS33_07 Datasheet, PDF (1/23 Pages) Texas Instruments – HIGH-SPEED DIFFERENTIAL RECEIVERS

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SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004
HIGH-SPEED DIFFERENTIAL RECEIVERS
FEATURES
• 400-Mbps Signaling Rate⁽¹⁾ and 200-Mxfr/s
Data Transfer Rate
• Operates With a Single 3.3-V Supply
• -4 V to 5 V Common-Mode Input Voltage
Range
• Differential Input Thresholds <±50 mV With 50
mV of Hysteresis Over Entire Common-Mode
Input Voltage Range
• Integrated 110-Ω Line Termination Resistors
On LVDT Products
• TSSOP Packaging (33 Only)
• Complies With TIA/EIA-644 (LVDS)
• Active Failsafe Assures a High-Level Output
With No Input
• Bus-Pin ESD Protection Exceeds 15 kV HBM
• Input Remains High-Impedance on Power
Down
• TTL Inputs Are 5 V Tolerant
• Pin-Compatible With the AM26LS32,
SN65LVDS32B, µA9637, SN65LVDS9637B
(1) _{The signalling rate of a line, is the number of voltage transitions}
that are made per second expressed in the units bps (bits per
second).
DESCRIPTION
This family of four LVDS data line receivers offers the
widest common-mode input voltage range in the
industry. These receivers provide an input voltage
range specification compatible with a 5-V PECL
signal as well as an overall increased ground-noise
tolerance. They are in industry standard footprints
with integrated termination as an option.
Precise control of the differential input voltage
thresholds allows for inclusion of 50 mV of input
voltage hysteresis to improve noise rejection on
slowly changing input signals. The input thresholds
are still no more than ±50 mV over the full input
common-mode voltage range.
The high-speed switching of LVDS signals usually
necessitates the use of a line impedance matching
resistor at the receiving-end of the cable or
transmission media. The SN65LVDT series of
receivers eliminates this external resistor by
integrating it with the receiver. The nonterminated
SN65LVDS series is also available for multidrop or
other termination circuits.
SN65LVDS33D, SN65LVDT33D
SN65LVDS33PW, SN65LVDT33PW
D OR PW PACKAGE
(TOP VIEW)
1B 1
1A 2
1Y 3
G4
2Y 5
2A 6
2B 7
GND 8
16 V_CC
15 4B
14 4A
13 4Y
12 G
11 3Y
10 3A
9 3B
logic diagram (positive logic)
G
G
SN65LVDT33 ONLY
1A
1Y
1B
2A
2Y
2B
3A
3Y
3B
4A
4Y
4B
SN65LVDS34D, SN65LVDT34D
D PACKAGE
(TOP VIEW)
logic diagram (positive logic)
V_CC 1
8 1A
1Y 2
7 1B
1A
1Y
2Y 3
6 2A
1B
GND 4
5 2B ^{SN65LVDT34 ONLY}
2A
2Y
2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2004, Texas Instruments Incorporated