SN65LVDS32B_07 Datasheet, PDF (1/20 Pages) Texas Instruments – HIGH-SPEED DIFFERENTIAL RECEIVERS

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SN65LVDS32B, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
HIGH-SPEED DIFFERENTIAL RECEIVERS
FEATURES
• Meets or Exceeds the Requirements of ANSI
EIA/TIA-644 Standard for Signaling Rates ⁽¹⁾ up
to 400 Mbps
• Operates With a Single 3.3-V Supply
• –2-V to 4.4-V Common-Mode Input Voltage
Range
• Differential Input Thresholds <50 mV With
50 mV of Hysteresis Over Entire Common-
Mode Input Voltage Range
• Integrated 110-Ω Line Termination Resistors
Offered With the LVDT Series
• Propagation Delay Times 4 ns (typ)
• Active Fail Safe Assures a High-Level Output
With No Input
• Bus-Pin ESD Protection Exceeds 15 kV HBM
• Inputs Remain High-Impedance on Power
Down
• Recommended Maximum Parallel Rate of
200 M-Transfer/s
• Available in Small-Outline Package With
1,27-mm Terminal Pitch
• Pin-Compatible With the AM26LS32, MC3486,
or µA9637
DESCRIPTION
This family of differential line receivers offers
improved performance and features that implement
the electrical characteristics of low-voltage differential
signaling (LVDS). LVDS is defined in the
TIA/EIA-644 standard. This improved performance
represents the second generation of receiver
products for this standard, providing a better overall
solution for the cabled environment. This generation
of products is an extension to TI's overall product
portfolio and is not necessarily a replacement for
older LVDS receivers.
D PACKAGE
(TOP VIEW)
SN65LVDS32B
SN65LVDT32B
Logic Diagram
(positive logic)
1B 1
1A 2
16 V_CC
15 4B
G
G
SN65LVDT32B
1Y 3 14 4A
ONLY (4 Places)
1A
G 4 13 4Y
1Y
2Y 5 12 G
1B
2A 6 11 3Y
2A
2B 7 10 3A
2Y
GND 8
9 3B
2B
3A
3Y
3B
4A
4Y
4B
SN65LVDS3486B
SN65LVDT3486B
D PACKAGE
Logic Diagram
(TOP VIEW)
(positive logic)
SN65LVDT3486B
1B 1
16 V_CC
ONLY (4 Places)
1A 2 15 4B
1A
1Y
1Y 3 14 4A
1B
1,2EN 4
13 4Y
1,2EN
2Y 5 12 3,4EN
2A
2Y
2A 6 11 3Y
2B
2B 7 10 3A
GND 8
9 3B
3A
3Y
3B
3,4EN
4A
4Y
4B
SN65LVDS9637B
SN65LVDT9637B
D PACKAGE
(TOP VIEW)
Logic Diagram
(positive logic)
V_CC 1
8 1A
1Y 2
7 1B
1A
1Y
2Y 3
6 2A
1B
GND 4
5 2B
SN65LVDT9637B
ONLY
2A
2Y
2B
(1) Signaling rate, 1/t, where t is the minimum unit interval and is
expressed in the units bit/s (bits per second).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2007, Texas Instruments Incorporated