SN65LVDS306 Datasheet, PDF (1/31 Pages) Texas Instruments – PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

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SN65LVDS306
SLLS765B – SEPTEMBER 2006 – REVISED FEBRUARY 2007
PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
FEATURES
• Serial Interface Technology
• Compatible With FlatLink™3G Such as
SN65LVDS305
• Supports Video Interfaces up to 24-Bit RGB
Data and 3 Control Bits Received Over One
SubLVDS Differential Line
• SubLVDS Differential Voltage Levels
• Up to 405-Mbps Data Throughput
• Three Operating Modes to Conserve Power
– Active mode QVGA: 17 mW
– Typical Shutdown: 0.7 μW
– Typical Standby Mode: 27 μW Typical
• Bus-Swap Function for PCB-Layout Flexibility
• ESD Rating > 4 kV (HBM)
• Pixel Clock Range of 4 MHz–15 MHz
• Failsafe on all CMOS Inputs
• Packaged in 5-mm × 5-mm MicroStar Junior
μBGA^® With 0,5-mm Ball Pitch
• Very Low EMI Meets SAE J1752/3 Kh-Spec
APPLICATIONS
• Small Low-Emission Interface Between
Graphics Controller and LCD Display
• Mobile Phones and Smart Phones
• Portable Multimedia Players
DESCRIPTION
The SN65LVDS306 receiver deserializes
FlatLink™3G-compliant serial input data to 27
parallel data outputs. The SN65LVDS306 receiver
contains one shift register to load 30 bits from one
serial input and latches the 24 pixel bits and 3 control
bits out to the parallel CMOS outputs after checking
the parity bit. If the parity check confirms correct
parity, the channel parity error (CPE) output remains
low. If a parity error is detected, the CPE output
generates a high pulse while the data output bus
disregards the newly-received pixel. Instead, the last
data word is held on the output bus for another clock
cycle.
The serial data and clock are received via
sub-low-voltage differential signalling (SubLVDS)
lines. The SN65LVDS306 supports three operating
power modes (shutdown, standby, and active) to
conserve power.
When receiving, the PLL locks to the incoming clock
CLK and generates an internal high-speed clock at
the line rate of the data line. The data is serially
loaded into a shift register using the internal
high-speed clock. The deserialized data is presented
on the parallel output bus with a recreation of the
pixel clock, PCLK, generated from the internal
high-speed clock. If no input CLK signal is present,
the output bus is held static with PCLK and DE held
low, while all other parallel outputs are pulled high.
The parallel (CMOS) output bus offers a bus-swap
feature. The SWAP control pin controls the output
pin order of the output pixel data to be either R[7:0].
G[7:0], B[7:0], VS, HS, DE or B[0:7], G[0:7], R[0:7],
VS, HS, DE. This gives a PCB designer the flexibility
to better match the bus to the LCD driver pinout or to
put the receiver device on the top side or the bottom
side of the PCB. The F/S control input selects
between a slow CMOS bus output rise time for best
EMI and power consumption and a fast CMOS
output for increased speed or higher-load designs.
Flatlinkä3G
123
456
789
*^0#
LCD
Driver
LVDS306
CLK DATA
LVDS305
Application
Processor
with
RGB
Video
Interface
M0056-02
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
μBGA is a registered trademark of Tessera, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated