SN65LVDS303 Datasheet, PDF (1/30 Pages) Texas Instruments – PROGRAMMABLE 27-BIT DISPLAY SERIAL-INTERFACE TRANSMITTER

SN65LVDS303
www.ti.com
SLLS743A – JULY 2006 – REVISED JANUARY 2007
PROGRAMMABLE 27-BIT DISPLAY SERIAL-INTERFACE TRANSMITTER
FEATURES
• FlatLink™3G Serial-Interface Technology
• Compatible With FlatLink3G Receivers Such
as SN65LVDS304
• Input Supports 24-bit RGB Video Mode
Interface
• 24-Bit RGB Data, 3 Control Bits, 1 Parity Bit
and 2 Reserved Bits Transmitted over 1 or 2
Differential Lines
• SubLVDS Differential Voltage Levels
• Effective Data Throughput up to 810 Mbps
• Three Operating Modes to Conserve Power
– Active-Mode QVGA 17.4 mW (typ)
– Active-Mode VGA 28.8 mW (typ)
– Shutdown Mode ≈ 0.5 µA (typ)
– Standby Mode ≈ 0.5 µA (typ)
• Bus Swap for Increased PCB Layout
Flexibility
• 1.8-V Supply Voltage
• ESD Rating > 2 kV (HBM)
• Typical Application: Host-Controller to
Display-Module Interface
• Pixel Clock Range of 4 MHz–30 MHz
• Failsafe on All CMOS Inputs
• Packaging: 80-Terminal, 5-mm × 5-mm µBGA^®
DESCRIPTION
The SN65LVDS303 serializer device converts 27
parallel data inputs to one or two sub-low-voltage
differential signaling (SubLVDS) serial outputs. It
loads a shift register with 24 pixel bits and 3 control
bits from the parallel CMOS input interface. In
addition to the 27 data bits, the device adds a parity
bit and two reserved bits into a 30-bit data word.
Each word is latched into the device by the pixel
clock (PCLK). The parity bit (odd parity) allows a
receiver to detect single bit errors. The serial shift
register is uploaded at 30 or 15 times the pixel-clock
data rate, depending on the number of serial links
used. A copy of the pixel clock is output on a
separate differential output.
FPC cabling typically interconnects the
SN65LVDS303 with the display. Compared to
parallel signaling, the SN65LVDS303 outputs
significantly reduce the EMI of the interconnect by
over 20 dB.
The SN65LVDS303 supports three power modes
(shutdown, standby and active) to conserve power.
When transmitting, the PLL locks to the incoming
pixel clock, PCLK, and generates an internal
high-speed clock at the line rate of the data lines.
The parallel data are latched on the rising or falling
edge of PCLK, as selected by the external control
signal CPOL. The serialized data is presented on the
serial outputs D0 and D1, together with a recreated
PCLK that is generated from the internal high-speed
clock and output on CLK. If PCLK stops, the device
enters a standby mode to conserve power.
The parallel (CMOS) input bus offers a bus-swap
feature. The SWAP terminal configures the input
order of the pixel data to be either R[7:0], G[7:0],
B[7:0], VS, HS, DE or B[0:7]. G[0:7], R[0:7], VS, HS,
DE. This gives a PCB designer the flexibility to better
match the bus to the host controller pinout or to put
the transmitter device on the top side or the bottom
side of the PCB.
Flatlinkä3G
123
456
789
*^0#
LCD
Driver
LVDS304
CLK DATA
LVDS303
Application
Processor
with
RGB
Video
Interface
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
µBGA is a registered trademark of Tessera, Inc..
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated