SN65LVDS301_08 Datasheet, PDF (1/34 Pages) Texas Instruments – PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER

SN65LVDS301
www.ti.com
SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006
PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER
FEATURES
• FlatLink™3G serial interface technology
• Compatible with FlatLink3G receivers such as
SN65LVDS302
• Input supports 24-bit RGB video mode
interface
• 24-Bit RGB Data, 3 Control Bits, 1 Parity Bit
and 2 Reserved Bits Transmitted over 1, 2 or 3
Differential Lines
• SubLVDS Differential Voltage Levels
• Effective Data Throughput up to 1755 Mbps
• Three Operating Modes to Conserve Power
– Active-Mode QVGA 17.4 mW (typ)
– Active-Mode VGA 28.8 mW (typ)
– Shutdown Mode ≈ 0.5 µA (typ)
– Standby Mode ≈ 0.5 µA (typ)
• Bus Swap for Increased PCB Layout
Flexibility
• 1.8-V Supply Voltage
• ESD Rating > 2 kV (HBM)
• Typical Application: Host-Controller to
Display-Module Interface
• Pixel Clock Range of 4 MHz–65 MHz
• Failsafe on all CMOS Inputs
• Packaging: 80 Pin 5mm × 5mm µBGA^®
• Very low EMI meets SAE J1752/3 'M'-spec
DESCRIPTION
The SN65LVDS301 serializer device converts 27
parallel data inputs to 1, 2, or 3 Sub Low-Voltage
Differential Signaling (SubLVDS) serial outputs. It
loads a shift register with 24 pixel bits and 3 control
bits from the parallel CMOS input interface. In
addition to the 27 data bits, the device adds a parity
bit and two reserved bits into a 30-bit data word.
Each word is latched into the device by the pixel
clock (PCLK). The parity bit (odd parity) allows a
receiver to detect single bit errors. The serial shift
register is uploaded at 30, 15, or 10 times the
pixel-clock data rate depending on the number of
serial links used. A copy of the pixel clock is output
on a separate differential output.
FPC cabling typically interconnects the
SN65LVDS301 with the display. Compared to
parallel signaling, the LVDS301 outputs significantly
reduce the EMI of the interconnect by over 20 dB.
The electromagnetic emission of the device itself is
very low and meets the meets SAE J1752/3
'M'-spec. (see Figure 37)
The SN65LVDS301 supports three power modes
(Shutdown, Standby and Active) to conserve power.
When transmitting, the PLL locks to the incoming
pixel clock PCLK and generates an internal
high-speed clock at the line rate of the data lines.
The parallel data are latched on the rising or falling
edge of PCLK as selected by the external control
signal CPOL. The serialized data is presented on the
serial outputs D0, D1, D2 with a recreated PCLK
generated from the internal high-speed clock, output
on the CLK output. If PCLK stops, the device enters
a standby mode to conserve power
The parallel (CMOS) input bus offers a bus-swap
feature. The SWAP pin configures the input order of
the pixel data to be either R[7:0]. G[7:0], B[7:0], VS,
HS, DE or B[0:7]. G[0:7], R[0:7], VS, HS, DE. This
gives a PCB designer the flexibility to better match
the bus to the host controller pinout or to put the
transmitter device on the top side or the bottom side
of the PCB.
Flatlinkä3G
123
456
789
*^0#
LCD
Driver
LVDS302
CLK DATA
LVDS301
Application
Processor
with
RGB
Video
Interface
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
µBGA is a registered trademark of Tessera, Inc..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated