SN65LVDS16_07 Datasheet, PDF (1/18 Pages) Texas Instruments – 2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

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SN65LVDS16, SN65LVP16
SN65LVDS17, SN65LVP17
SLLS625B – SEPTEMBER 2004 – REVISED NOVEMBER 2005
2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS
FEATURES
• Low-Voltage PECL Input and Low-Voltage
PECL or LVDS Outputs
• Clock Rates to 2 GHz
– 140-ps Output Transition Times
– 0.11 ps Typical Intrinsic Phase Jitter
– Less than 630 ps Propagation Delay Times
• 2.5-V or 3.3-V Supply Operation
• 2-mm × 2-mm Small-Outline
No-Lead Package
APPLICATIONS
• PECL-to-LVDS Translation
• Clock Signal Amplification
DESCRIPTION
These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain
outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on
the SN65LVx16) and fully differential inputs on the SN65LVx17.
The SN65LVx16 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV
either by leaving it open (NC), grounded, or tied to V_CC. (When left open, the Q output defaults to 575 mV.) The
Q on the SN65LVx17 defaults to 575 mV as well.
Both devices provide a voltage reference (V_BB) of typically 1.35 V below V_CC for use in receiving single-ended
PECL input signals. When not used, V_BB should be unconnected or open.
All devices are characterized for operation from –40°C to 85°C.
SN65LVDS16, SN65LVP16
Q
4 mA
SN65LVDS17, SN65LVP17
Q
4 mA
A
V_BB
GC
V_REF
V_CC
Y
A
Z
B
V_BB
EN
Y
Z
V_REF
V_CC
EN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated