SN65LVDS116DGGR Datasheet, PDF (1/19 Pages) Texas Instruments – 16-PORT LVDS REPEATER

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SN65LVDS116
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
16-PORT LVDS REPEATER
FEATURES
• One Receiver and Sixteen Line Drivers Meet
or Exceed the Requirements of ANSI
EIA/TIA-644 Standard
• Typical Data Signaling Rates to 400 Mbps or
Clock Frequencies to 400 MHz
• Enabling Logic Allows Separate Control of
Each Bank of Four Channels or 2-Bit
Selection of Any One of the Four Banks
• Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a 100-Ω
Load
• Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Termination Networks
• Propagation Delay Times < 4.7 ns
• Output Skew Is < 300 ps and Part-to-Part
Skew < 1.5 ns
• Total Power Dissipation Typically 470 mW
With All Ports Enabled and at 200 MHz
• Driver Outputs or Receiver Input Is High
Impedance When Disabled or With V_CC < 1.5
V
• Bus-Pin ESD Protection Exceeds 12 kV
• Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
DESCRIPTION
The SN65LVDS116 is one differential line receiver
connected to sixteen differential line drivers that
implement the electrical characteristics of low-voltage
differential signaling (LVDS). LVDS, as specified in
EIA/TIA-644, is a data signaling technique that offers
the low-power, low-noise coupling, and fast switching
speeds to transmit data at relatively long distances.
(Note: The ultimate rate and distance of data transfer
is dependent upon the attenuation characteristics of
the media, the noise coupling to the environment, and
other system characteristics.)
The intended application of this device and signaling
technique is for point-to-point or multidrop baseband
data transmission over controlled impedance media
of approximately 100 Ω. The transmission media may
be printed-circuit board traces, backplanes, or cables.
The large number of drivers integrated into the same
substrate along with the low pulse skew of balanced
signaling, allows extremely precise timing alignment
of the signals repeated from the input. This is
particularly advantageous in system clock distribution.
The SN65LVDS116 is characterised for operation
from –40°C to 85°C.
DGG PACKAGE
(TOP VIEW)
GND ₁
V_{CC 2}
V_CC 3
GND ₄
ENA ₅
ENA ₆
NC ₇
NC 8
NC 9
ENB 10
ENB ₁₁
NC ₁₂
NC ₁₃
NC 14
GND 15
V_CC 16
V_CC 17
GND ₁₈
A 19
B 20
NC 21
ENC 22
ENC 23
S0 24
S1 25
SM 26
END 27
END 28
GND 29
V_CC 30
V_CC 31
GND 32
64 ^A1Y
63 ^A1Z
62 A2Y
61 ^A2Z
60 ^A3Y
59 ^A3Z
58 ^A4Y
57 A4Z
56 B1Y
55 B1Z
54 ^B2Y
53 ^B2Z
52 ^B3Y
51 B3Z
50 B4Y
49 B4Z
48 C1Y
47 ^C1Z
46 C2Y
45 C2Z
44 C3Y
43 C3Z
42 C4Y
41 C4Z
40 D1Y
39 D1Z
38 D2Y
37 D2Z
36 D3Y
35 D3Z
34 D4Y
33 D4Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2005, Texas Instruments Incorporated