SN65LVDS116 Datasheet, PDF (1/16 Pages) Texas Instruments – 16-PORT LVDS REPEATER

SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
D One Receiver and Sixteen Line Drivers
Meet or Exceed the Requirements of ANSI
DGG PACKAGE
(TOP VIEW)
EIA/TIA-644 Standard
D Designed for Signaling Rates Up to
622 Mbps
D Enabling Logic Allows Separate Control of
Each Bank of Four Channels or 2-Bit
Selection of Any One of the Four Banks
D Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100 Ω Load
D Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Termination Networks
D Propagation Delay Times <4.7 ns
D Output Skew is < 300 ps and Part-to-Part
GND ₁
V_{CC 2}
V_{CC 3}
GND ₄
ENA ₅
ENA ₆
NC ₇
NC ₈
NC ₉
ENB ₁₀
ENB ₁₁
NC ₁₂
NC ₁₃
NC ₁₄
GND ₁₅
64 ^A1Y
63 ^A1Z
62 ^A2Y
61 ^A2Z
60 ^A3Y
59 ^A3Z
58 ^A4Y
57 ^A4Z
56 ^B1Y
55 ^B1Z
54 ^B2Y
53 ^B2Z
52 ^B3Y
51 ^B3Z
50 ^B4Y
Skew <1.5 ns
V_{CC 16 49} B4Z
D Total Power Dissipation Typically 470 mW
With All Ports Enabled and at 200 MHz
D Driver Outputs or Receiver Input is High
Impedance when Disabled or With
V_CC <1.5 V
D Bus-Pin ESD Protection Exceeds 12 kV
D Packaged in Thin Shrink Small-Outline
V_{CC 17}
GND ₁₈
A ₁₉
B ₂₀
NC ₂₁
ENC ₂₂
ENC 23
S0 24
48 ^C1Y
47 ^C1Z
46 ^C2Y
45 ^C2Z
44 ^C3Y
43 ^C3Z
42 C4Y
41 C4Z
Package With 20 Mil Terminal Pitch
S1 25 40 D1Y
description
SM 26
END 27
39 D1Z
38 D2Y
The SN65LVDS116 is one differential line reciever
connected to sixteen differential line drivers that
implement the electrical characteristics of
low-voltage differential signaling (LVDS). LVDS,
as specified in EIA/TIA-644, is a data signaling
END 28
GND 29
V_CC 30
V_CC 31
GND 32
37 D2Z
36 D3Y
35 D3Z
34 D4Y
33 D4Z
technique that offers the low-power, low-noise
coupling, and switching speeds to transmit data at speeds up to 622 Mbps and relatively long distances. (Note:
The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media,
the noise coupling to the environment, and other system characteristics.)
The intended application of this device and signaling technique is for point-to-point or multidrop baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed
circuit board traces, backplanes, or cables. The large number of drivers integrated into the same substrate along
with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated
from the input. This is particularly advantageous in system clock distribution.
The SN65LVDS116 is characterised for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1999, Texas Instruments Incorporated
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