SN65LVDS109 Datasheet, PDF (1/19 Pages) Texas Instruments – DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
D Two Line Receivers and Eight (’109) or
Sixteen (’117) Line Drivers Meet or Exceed
the Requirements of ANSI EIA/TIA-644
Standard
D Designed for Signaling Rates up to 632
Mbps
D Outputs Arranged in Pairs From Each Bank
D Enabling Logic Allows Individual Control of
Each Driver Output Pair, Plus all Outputs
D Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100Ω Load
D Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Termination Networks
D Propagation Delay Times < 4.5 ns
D Output Skew Less Than 550 ps
Bank Skew Less Than 150 ps
Part-to-Part Skew Less Than 1.5 ns
D Total Power Dissipation Typically < 500 mW
With All Ports Enabled and at 200 MHz
D Driver Outputs or Receiver Input Equals
High Impedance When Disabled or With
V_CC < 1.5 V
D Bus-Pin ESD Protection Exceeds 12 kV
D Packaged in Thin Shrink Small-Outline
Package With 20 mil Terminal Pitch
description
The SN65LVDS109 and SN65LVDS117 are
configured as two identical banks, each bank
having one differential line receiver connected to
either four (’109) or eight (’117) differential line
drivers. The outputs are arranged in pairs having
one output from each of the two banks. Individual
output enables are provided for each pair of
outputs and an additional enable is provided for all
outputs.
SN65LVDS109
DBT PACKAGE
(TOP VIEW)
GND ₁
V_{CC 2}
GND ₃
NC ₄
ENM ₅
ENA ₆
ENB 7
1A 8
1B 9
GND 10
2A 11
2B 12
ENC 13
END 14
NC 15
NC 16
GND 17
V_CC 18
GND 19
38 ^A1Y
37 ^A1Z
36 ^A2Y
35 ^A2Z
34 ^NC
33 ^B1Y
32 ^B1Z
31 ^B2Y
30 ^B2Z
29 ^NC
28 ^C1Y
27 ^C1Z
26 ^C2Y
25 ^C2Z
24 NC
23 D1Y
22 D1Z
21 D2Y
20 D2Z
SN65LVDS117
DGG PACKAGE
(TOP VIEW)
GND ₁
V_{CC 2}
V_{CC 3}
GND ₄
NC ₅
ENM ₆
ENA ₇
ENB ₈
ENC ₉
END ₁₀
NC ₁₁
GND ₁₂
1A ₁₃
1B ₁₄
GND ₁₅
V_{CC 16}
V_{CC 17}
GND ₁₈
2A ₁₉
2B ₂₀
GND ₂₁
NC ₂₂
ENE 23
ENF 24
ENG 25
ENH 26
NC 27
NC 28
GND 29
V_CC 30
V_CC 31
GND 32
64 ^A1Y
63 ^A1Z
62 ^A2Y
61 ^A2Z
60 ^B1Y
59 ^B1Z
58 ^B2Y
57 ^B2Z
56 ^C1Y
55 ^C1Z
54 ^C2Y
53 ^C2Z
52 ^D1Y
51 ^D1Z
50 ^D2Y
49 ^D2Z
48 ^E1Y
47 ^E1Z
46 ^E2Y
45 ^E2Z
44 ^F1Y
43 ^F1Z
42 F2Y
41 F2Z
40 G1Y
39 G1Z
38 G2Y
37 G2Z
36 H1Y
35 H1Z
34 H2Y
33 H2Z
The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling
(LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise
emission, high noise immunity, and high switching speeds. It can be used to transmit data at speeds up to at
least 622 Mbps and over relatively long distances. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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