SN65LVDS104_07 Datasheet, PDF (1/26 Pages) Texas Instruments – 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

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SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
FEATURES
• Receiver and Drivers Meet or Exceed the
Requirements of ANSI EIA/TIA-644 Standard
– SN65LVDS105 Receives Low-Voltage TTL
(LVTTL) Levels
– SN65LVDS104 Receives Differential Input
Levels, ±100 mV
• Typical Data Signaling Rates to 400 Mbps or
Clock Frequencies to 400 MHz
• Operates From a Single 3.3-V Supply
• Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a 100-Ω
Load
• Propagation Delay Time
– SN65LVDS105 – 2.2 ns (Typ)
– SN65LVDS104 – 3.1 ns (Typ)
• LVTTL Levels Are 5-V Tolerant
• Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Networks
• Driver Outputs Are High Impedance When
Disabled or With V_CC <1.5 V
• Bus-Pin ESD Protection Exceeds 16 kV
• SOIC and TSSOP Packaging
DESCRIPTION
The SN65LVDS104 and SN65LVDS105 are a differ-
ential line receiver and a LVTTL input (respectively)
connected to four differential line drivers that im-
plement the electrical characteristics of low-voltage
differential signaling (LVDS). LVDS, as specified in
EIA/TIA-644 is a data signaling technique that offers
low-power, low-noise coupling, and switching speeds
to transmit data at relatively long distances. (Note:
The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the
media, the noise coupling to the environment, and
other system characteristics.)
SN65LVDS104
D OR PW PACKAGE
(Marked as LVDS104)
(TOP VIEW)
EN1 1
EN2 2
EN3 3
V_CC 4
GND 5
A6
B7
EN4 8
16 1Y
15 1Z
14 2Y
13 2Z
12 3Y
11 3Z
10 4Y
9 4Z
SN65LVDS105
D OR PW PACKAGE
(Marked as LVDS105)
(TOP VIEW)
EN1 1
EN2 2
EN3 3
V_CC 4
GND 5
A6
NC 7
EN4 8
16 1Y
15 1Z
14 2Y
13 2Z
12 3Y
11 3Z
10 4Y
9 4Z
logic diagram (positive logic)
’LVDS104
1Y
1Z
EN1
EN2
2Y
2Z
EN3
3Y
A
3Z
B
4Y
4Z
EN4
’LVDS105
1Y
1Z
EN1
EN2
2Y
2Z
EN3
3Y
3Z
A
4Y
4Z
EN4
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse
skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input.
This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2005, Texas Instruments Incorporated