SN65LVDS049 Datasheet, PDF (1/11 Pages) Texas Instruments – DUAL LVDS DIFFERENTIAL DRIVERS AND RECEIVERS

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5,0 mm x 6,4 mm
SN65LVDS049
SLLS575 – AUGUST 2003
DUAL LVDS DIFFERENTIAL DRIVERS AND RECEIVERS
FEATURES
• DS90LV049 Compatible
• Up to 400 Mbps Signaling Rates
• Flow-Through Pin-out
• 50 ps Driver Channel-to-Channel Skew (Typ)
• 50 ps Receiver Channel-to-Channel Skew
(Typ)
• 3.3-V Power Supply
• High-Impedance Disable for all Outputs
• Internal Failsafe Biasing of Receiver Inputs
• 1.4 ns Driver Propagation Delay (Typ)
• 1.9 ns Receiver Propagation Delay (Typ)
• High Impedance Bus Pins on Power Down
• ANSI TIA/EIA-644-A Compliant
• Receiver Input and Driver Output ESD Ex-
ceeds 10 kV
• 16-pin TSSOP Package
APPLICATIONS
• Full-duplex LVDS Communications of Clock
and Data
• Printers
DESCRIPTION
The SN65LVDS049 is a dual flow-through differential
line driver-receiver pair that uses low-voltage differen-
tial signaling (LVDS) to achieve signaling rates as high
as 400 Mbps. The TIA/EIA-644-A standard compliant
electrical interface provides a minimum differential out-
put voltage magnitude of 250 mV into a 100-Ω load and
receipt of signals with up to 1 V of ground potential
difference between a transmitter and receiver. The
LVDS receivers have internal failsafe biasing that
places the outputs into a known high state for uncon-
nected differential inputs.
The intended application of this device and signaling
technique is for point-to-point baseband data trans-
mission over controlled impedance media of approxi-
mately 100-Ω characteristic impedance. The trans-
mission media may be printed-circuit board traces,
backplanes, or cables. (Note: The ultimate rate and
distance of data transfer is dependent upon the attenu-
ation characteristics of the media, the noise coupling to
the environment, and other application specific charac-
teristics)
The SN65LVDS049 is characterized for operation from
–40°C to 85°C
FUNCTIONAL DIAGRAM
R_IN1−
R_IN1+
R1
R_OUT1
R_IN2+
R_IN2−
R2
R_OUT2
D_OUT2−
D_OUT2+
D2
D_IN2
D_OUT1+
D_OUT1−
D1
D_IN1
AND
EN
EN
PW PACKAGE (Marked as LVDS049)
(TOP VIEW)
R_{IN1 -}
1
R_IN1+
2
R_IN2+
3
R_{IN2 -}
4
D_{OUT2 -}
5
D_OUT2+
6
D_OUT1+
7
D_{OUT1 -}
8
16
EN
15
R_OUT1
14
R_OUT2
13
GND
12
V_CC
11
D_IN2
10
D_IN1
9
EN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily in-
clude testing of all parameters.
Copyright © 2003, Texas Instruments Incorporated